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Here is image showing a basic write transfer:

enter image description here

  1. The HWDATA comes 1 clk cycle after the control signals and the address. Why is this so?
  2. What will happen if the HWDATA is put on the bus at the same time as the address and control signals and kept there?
  3. Is it true that the address, control signals, and the HWDATA must be kept on bus for only 1 clk cycle and then be reset to zeros?
gyuunyuu
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1 Answers1

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What will happen if the HWDATA is put on the bus at the same time as the address and control signals and kept there?

I've added four labels to your diagram.

Is it true that the address, control signals, and the HWDATA must be kept on bus for only 1 clk cycle and then be reset to zeros?

They are "Don't care" labels: -

enter image description here

The HWDATA comes 1 clk cycle after the control signals and the address. Why is this so?

Possibly because the address needs to be set up one HCLK cycle earlier and clocked in on the falling edge of HCLK with the next falling edge being reserved for data. It's just the way it is without trying to examine the actual circuit.

Andy aka
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