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I've got an obsolete part in a design (SY100S839VZG) that is being used to take a single 100MHz clk and divide it down into two PECL p/n pairs.

For the life of me, I cannot seem to find a single clock divider out there that supports /5 that isn't obsolete or about to be. Did the clocking industry collectively decide to longer support that, or am I just missing something obvious?

I've checked Silicon Labs, Texas Instruments, Analog Devices, ON Semiconductor, and Renesas, along with Digikey/Mouser/etc.

Any ideas or suggestions on where to go from here?

Daniel
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    Maybe they went the route of programmable PLLs? I know that SiLabs makes such ICs. – jaskij Jan 24 '20 at 16:03
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    I'm pretty sure the modern way of doing this is to use a programmable PLL, but I'm no expert. – Hearth Jan 24 '20 at 16:04
  • There are tons of logic chips dividing by 5. Did you check their slew rates for compatibility? Do you even need low skew in your particular application? Also, even if the divider's output is not satisfactory, I am sure you can find suitable schmitt buffer to condition the signal – Maple Jan 24 '20 at 16:05
  • In the past I have used Cypress programmable devices for this sort of thing; they even provide a tool to calculate the correct divisors. https://www.cypress.com/documentation/software-and-drivers/cyberclocks-r32100 – Peter Smith Jan 24 '20 at 16:32
  • @Maple Unfortunately, most of the logic chips that I have found aren't suitable for the frequencies I'm running. And then there is the whole issue of having to implement a differential driver for the output which is more unique parts. This design is pretty tight already and so I would ideally like to replace a single IC with another single IC. – Daniel Jan 24 '20 at 17:51

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