0

Could someone explain how HLS treats arrays that are declared constants? I declare an array as:

const uint8 myArray [100][100] = {....};

and then access the array by element in the loop. According to the UG902 on p.328, such array is implemented as a ROM and consequently I need to partition it to get more reads in the clock cycle. Why would HLS implement this array as a ROM and use resources instead of converting it to ties of VCCs and GNDs? Do I need to explicitly tell HLS to implement it as ties to VCC and GND?

Nazar
  • 3,142
  • 4
  • 35
  • 62

1 Answers1

0

First, FPGAs can't arbitrarily configure single transistors to do things such as making a tie. An ASIC designer can, but an ASIC is not an FPGA.

"Why would HLS implement this array as a ROM and use resources instead of converting it to ties of VCCs and GNDs?"

In your mind, what is constitutes a "ROM" bit in an FPGA? Is it a transistor pair in a push-pull configuration that connects the common node to either Vcc or GND? Let's assume it is. So what is driving the gates of those transistors so the stack holds state? An SRAM? Well that's a bit pointless because now you need those two push-pull transistors plus six transistors for the SRAM. You might as well just use an SRAM.

If you don't use an SRAM, then you need to use configure a logic block as lookup table but those use many more transistors per bit, and can be used to do things other than just storing bits so its a waste.

An FPGA is not a sea of transistors you can individually manipulate. It's a sea of logic blocks.

DKNguyen
  • 54,733
  • 4
  • 67
  • 153
  • I thought that during implementation the constants are converted to ties (vcc, gnd). I can tie any Inputs to vcc or ground, so why couldn't I have an adder that takes in the first input from a variable (register), the the second input from a constant (tied wires to vcc/gnd)? – Nazar Dec 27 '19 at 18:31
  • @Nazar That's part of the design of the inputs on the logic block. It's not something you just do anywhere on the FPGA. So that little "tie" you are talking about has a huge logic block hanging off of it. It's not floating on its own and thus you cannot just arbitrarily connect to anything else in the FPGA with no waste. Also note that the configuration of the tie for that input (as well as the rest of the logic block) is ultimately stored in an SRAM cells anyways. – DKNguyen Dec 27 '19 at 18:37
  • I see. So I have a choice to declare 100*100 separate constant variables, or an array of [100][100]. Ignoring the C-code complexity ( three lines of code when using loop vs. writing out each operation explicitly on every constant) which one would take up more resources: the array[100][100] or 10,000 separate constants? – Nazar Dec 27 '19 at 18:39
  • @Nazar I would think they take up the same amount of resources. – DKNguyen Dec 27 '19 at 18:41
  • That's interesting. If I can store only 6 bits in SRAM cell, then I need two cells per 8-bit constant. Thus, to store 6 constants I would need 12 cells. Now, is it possible to make my ROM (composed of 8 SRAM cells) to have port with of 48bits? This way I would only need 8 cells to store 6 constants by sharing bits between cells? Is that even possible? – Nazar Dec 27 '19 at 18:53
  • @Nazar No, an SRAM cell takes six TRANSISTORS to build and stores ONE bit. That's why processors and a small amount of SRAM and lots of DRAM which only takes one transistor, but is slower, more power hungry, and needs to be refreshed. – DKNguyen Dec 27 '19 at 18:54