4017 IC block diagram

Question

I am really confused with the block diagram of 4017 IC. Here's the dataheet.

I really can't wrap my head around the way they have taken the output for each count. They are just taking two flip to choose the state. Shouldn't they take all four?

The outputs of flip-flops go through the AND gate (NAND+NOT).Let's take the count of 3 for illustration here. For this, the counter should have 0011 (Q4-Q3-Q2-Q1) in the flip-flops. In the block diagram, they have chosen only Q4' and Q3. This means the LED connected to count three should light up when the Q4 is low and Q3 is high ie. (01XX). But that't not what the flip-flops are holding.

Also there are 4 cases where the Q4 is low and Q3 is high. Counts of 4,5,6,7 have their 4th bit 0 and 3rd bit 1.

What is going on exactly inside the counter? You may take any count for the illustration.

I have attached the portion of datasheet for convenience:

Here's a decade counter that I have studied:

Cropped by Irfanview ^Y then copied ^C and pasted here ^V

Dave Tweed · Accepted Answer · 2019-12-20T17:08:17.427

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The FFs are not counting in binary, they're a Johnson (twisted ring) counter. This has the advantage that any given state can be decoded using a 2-input gate, which is exactly why they did it this way. Adding one extra FF is simpler than creating ten 4-input gates. And also, the outputs are guaranteed to be glitch-free, since only one FF changes state at a time. The ten output gates detect which FF is about to change state, by comparing input to output.

edited Dec 20 '19 at 17:08

answered Dec 20 '19 at 16:40

Dave Tweed

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That makes sense now. What if the no. of counts are more than 16? With 4-bits I can count from 0-15. What if I need more? How many bits should I take in account for decoding? – G-aura-V Dec 21 '19 at 04:24

score 3 · Answer 2 · answered Dec 20 '19 at 16:46

Both are Decade divide by 10 counters but instead of a HEX parallel coded output of the BCD counter, the Johnson counter makes a square wave divide by 10 and shifts the pattern to AND the input and output that produces the leading edge of 1 in 10 outputs being active.

There are many ways to do that and here is another.

score 2 · Answer 3 · answered Dec 20 '19 at 16:51

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The CD4017 is not a counter. Every datasheet in the world says it is, but inside it is not - it is a shift register. This completely changes the decoding needed to isolate each "count" state to a separate output pin.

If you follow the internal schematic with this in mind, you will see that the Q5 inverted output, which is a 1 after a Reset, is fed back to the first stage D input. For the first five counts after a reset, a 1 is shifted down the line. When it hits stage 5, the Q- output goes low, feeding a 0 into the first stage D input. This shifts down the line until stage 5 inverts it again and sends a 1 to stage 1.

If fact things are a bit more complex than that. There is some funky decoding logic before the third stage D input that I've never sorted out.

answered Dec 20 '19 at 16:51

AnalogKid

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The "funky logic" eliminates invalid states. – Dave Tweed Dec 20 '19 at 16:52
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as a 5 stage SR, it ends up being "five" divide by 10 binary counters each shifted by 1 Clk pulse or a 5 phase 1/10 internal counter . So it is both a SR and a counter. – Tony Stewart EE75 Dec 20 '19 at 16:53
Yeah, ring/twisted ring counters are still considered "counters" AIUI... – ThreePhaseEel Dec 21 '19 at 02:41

score 0 · Answer 4 · answered Dec 20 '19 at 16:43

The ultimate task of the chip is to produce an output sequence of 10 outputs 0..9 (plus carry).

There are many ways to do it and the designer(s) probably found that a decade counter would cost more logic (specially in the decoding of the outputs) then a different type of counter.

4017 IC block diagram

4 Answers4