In Intel's Pentium Processor Family Developer Manual, regarding the CPU clock, it says that "it is recommended that CLK begin toggling within 150 ms after VCC reaches its proper operating level. This recommendation is to ensure long-term reliability of the device."
From a circuit implementation perspective, how might holding the clock low or high damage the device?
The clock undoubtedly operates charge pumps within the chip that provide bias voltages for various functional areas. Without proper bias, leakage currents are probably higher than the transistors are really designed to handle long-term.
If tristate bus contention can occur, the shoot thru energy temperature rise would be of the same amount of time. It seems the power on reset is not enough.
Not necesarily a high or low clock affects sequence but it may actually miss several clock cycles initially due to device current stabilizing thus degrading overall long term availability due to spureous error
