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SR NOR Latch

Can someone please confirm if I understand this correctly: When neither R nor S are on (both are 0) it seems to me that at first both outputs are 1, then it feeds back through, and both go to 0, and then back to 1, infinitely?

But this assumes that all the signals travel precisely exactly as fast. As I understand it, in the real world there are teensy variations in the response times of the electronic components, which will lead to one of the outputs being stably on and the other being stably off. However, the collapse of the oscillating circuit is NOT due to the logic of the circuit, but the imperfections of the real world.

Again, as I understand it, if we had perfect components with no variations that could perfectly replicate the circuit in the image, then both outputs would oscillate between being on together and off together forever - or at least until R or S is set.

Now for the big question: is this 100% correct, or have I made a significant mistake? Because trying to understand the off-state of this circuit has been breaking my brain. (Just a regular fellow with no electronics experience here and a bit of understanding of logic.)

Sindyr
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    Welcome. Hint: Because these are NOR gates, they only respond to a '1' input, but for a rational output only R or S can be set to '1'. If R and S = 0 then nothing changes. Please don't trip over your brain on the simple stuff. Think it through. –  Nov 23 '19 at 23:45
  • This topic was covered quite well some time back, see this SE answer for more info on this: (https://electronics.stackexchange.com/questions/14653/what-is-the-beginning-state-for-q-in-a-sr-latch) – Nedd Nov 24 '19 at 00:20
  • when the latch starts oscillating, imbalances (transistors are never exactly matched; thermal noise is never exactly the same, because its random), in what is called "metastability", one output will come to dominate, and the latch will resolve into a stable state. – analogsystemsrf Nov 24 '19 at 03:51

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