2

I am routing a 16 bit ADC chip, the LTC2217 (datasheet) to FPGA. Each bit is an LVDS pair and I know +/- of the pair should be the same length but what about from pair to pair? I have 2 of these chips, 18 pairs, if you include OF and CLK, 36 pairs of LvDS having to be meandered to the same length becomes somewhat messy.

IE say bit 1 is 35mm and bit 0 is 37mm, how far off, if any are they allowed to be? I assume it has to do with sampling frequency, which for this chip is 105Msps.

Dave Tweed
  • 168,369
  • 17
  • 228
  • 393
TylerM
  • 23
  • 3

1 Answers1

2

The answer is driven by the output timing diagram of your ADC, shown here:

enter image description here

The chip provides a clock signal synchronized to the data. The clock falling edge is in the middle of the data valid interval as they leave the chip.

At maximum data rate, the clock period is about 10 ns.

This means you need to keep all your data signals aligned to the clock, with skew no more than 3 or 4 ns.

Since propagation velocity on the board is somewhere in the neighborhood of 40 cm / ns, this should be relatively easily achieved. To be tidy, I'd shoot for no more than 1 or 2 cm of trace length difference between any data signal and the clock.

The Photon
  • 126,425
  • 3
  • 159
  • 304
  • 1
    Thank you! and Thank you for the explanation! – TylerM Nov 20 '19 at 18:15
  • To have the lines have the same impedance, they need the same parasitics. Thus also match the closeness of traced. If squeeze 8 very close, then also squeeze all the others close. – analogsystemsrf Nov 21 '19 at 02:01