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I am trying to sketch the negative waveform of an OPAMP over here.

enter image description here

I am not sure how to proceed with this as I have usually seen OPAMP with dual power supply. But this one have +9V and ground.

My thinking to go about this problem :

  1. The voltage level at the positive terminal of OPAMP is +4.5V
  2. So, the voltage at Vout would also be +4.5V due to the 100k between between +ve and Vout
  3. As +4.5V is present at Vout, the 10nF capacitor which is connected to ground gets charged.
  4. As it gets charged to 4.5V, the output will will become 0V?
  5. So, the output will go to 0V?

Please tell me how to proceed from this?

  • Step 2 doesn't sound right. Why would Vout be 4.5 V specifically? – Dave Tweed Nov 02 '19 at 04:17
  • The 1k ohms in series with the voltage source will act as voltage divider and divide the voltage into half due to same resistance. And since, this line is connected to Vout through 100k resistor, the Vout will also be 4.5V right? If I am wrong, please explain clearly where I'm making a mistake –  Nov 02 '19 at 04:19
  • The 100k resistor has no direct influence on Vout. Remember, the basic function of an opamp is \$V_{out} = A_{openloop} (V_+ - V_-)\$. – Dave Tweed Nov 02 '19 at 04:23
  • Ok. Could you please explain your approach if my approach is wrong –  Nov 02 '19 at 04:26
  • Welcome to EE.SE! This appears to be a homework question. As such, you need to show us your work so far, and explain which part of the question you're having trouble with. For future reference: Homework questions on EE.SE enjoy/suffer a special treatment. We don't provide complete answers, we only provide hints or Socratic questions, and only when you have demonstrated sufficient effort of your own. Otherwise, we would be doing you a disservice, and getting swamped by homework questions at the same time. See also [here](http://meta.electronics.stackexchange.com/a/5120/7036). – Dave Tweed Nov 02 '19 at 04:32
  • Yes. i understand that. As you can clearly see my work done above in the steps. I have done my steps and mentioned where I have got stucked. –  Nov 02 '19 at 04:33
  • What I'm saying is, I'm not going to just hand you a complete solution; I'm going to try to lead you into discovering the solution on your own. The hint is, your idea about the output being 4.5 V is wrong -- can you work out a different number based on what I've said so far? – Dave Tweed Nov 02 '19 at 04:34
  • However, I'm going to bed now. I'll pick this up again in the morning. – Dave Tweed Nov 02 '19 at 04:36
  • Ok thanks. I am trying to understand what number would that be. But unable to figure out. Let me try –  Nov 02 '19 at 04:37
  • Will the Vout oscillate between +9V and 0V instead of 4.5V –  Nov 02 '19 at 05:26
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    yes, you have an oscillator – analogsystemsrf Nov 02 '19 at 06:22
  • Can you just explain a little more on this circuit on how it works –  Nov 02 '19 at 12:27
  • Try read this: http://www.learnabout-electronics.org/Oscillators/osc42.php – G36 Nov 02 '19 at 12:35
  • In the link shared above, i wan't not able to understand why the voltage on the negative terminal oscillates between 6V and 3V. I couldn't understand the R1, R2, R3 series and parallel combination. Can you explain that a bit. And in my diagram, my waveform will oscillate between 0 and 9V only right? –  Nov 03 '19 at 07:25
  • Just [simulating](http://tinyurl.com/y52qe8wu) it goes a long way. Great for finding out how it works. – Harry Svensson Nov 03 '19 at 14:10
  • @HarrySvensson , thanks for the simulation. Will attempt it from now on –  Nov 03 '19 at 16:20

1 Answers1

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In the circuit, you have posted the Opamp dos not work in a linear region.

More about the linear operation you can find here:

Op-amp: Virtual ground principle and other doubts

But instead of this, the opamp is working as a voltage comparator with hysteresis (positive feedback).

Here you can see a voltage comparator without positive feedback.

enter image description here

As you can see I use a voltage divider at non-inverting input to set up the reference voltage. The opamp will compare the input signal (\$V_{IN}\$) with the reference voltage (\$V_{REF}\$).

When the \$ V_{IN} > V_{REF}\$ the opamp output will drive to the negative supply, GND \$0V\$ in this example.

But when \$ V_{IN} < V_{REF}\$ the output will drive to the positive supply voltage, \$+9V\$ in this example.

enter image description here

Now lets us see what will happen if we add a positive feedback resistor connected between the output terminal (\$V_{OUT}\$) and non-inverting input (\$V_{REF}\$). And connect the \$V_{IN}\$ input the GND (\$0V\$).

enter image description here

What we know for sure is that \$ V_{IN} < V_{REF}\$, therefore, the output will be driven to the positive supply (\$+9V\$). Thanks to this we can simplify the circuit and find the new \$V_{REF}\$ value with this additional (\$R_3\$) resistor included. As you can see we have a new voltage divider and resistor \$R_1\$ and \$R_3\$ are connected in parallel. Hence the \$V_{REF}\$ voltage is equal to:
$$V_{UTP} = V_{CC} \cdot \frac{R_2}{(R_1||R_2)+R_2} = 9V \cdot \frac{1k\Omega}{500\Omega+1k\Omega} = 6V$$

With this new \$V_{REF}\$ we can say that as long as \$ V_{IN} < 6V\$ the output will be driven to the positive supply voltage, \$+9V\$. And that any input voltage larger than \$6V\$ will cause the output to transition to \$0V\$.

So, we can say that we have an Upper threshold point (voltage) equal to \$V_{UTP}=6V\$

But when the output is driven to the negative supply, GND \$0V\$, the \$R_3\$ resistor will now by in parallel with \$R_2\$. And this again will change the \$V_{REF}\$ voltage value.

enter image description here

$$V_{LTP} = V_{CC} \cdot \frac{R_2||R_3}{R_1+(R_2||R_3)} = 9V \cdot \frac{500\Omega}{1k\Omega+500\Omega} = 3V$$

This means that the input signal will have to be driven below a lower threshold point \$V_{LTP} = 3V\$ to cause the output to transition back again to \$9V\$.

As you can see adding a positive feedback resistor (\$R_3\$) slightly change how our voltage comparator works:
The input must now change above the upper threshold point (\$V_{UTP} = 6V\$) for the output to change (transition) to logic low (0V). Further increases in the input voltage don't change anything at the output. To any change at the output to occur the input voltage must start to decreases below the lower threshold point \$V_{LTP} = 3V\$ and the output will switch back to the logic high (\$9V\$). And again further decreases in the input voltage have no effect on the output state. As you can see our new circuit has now two distinguish threshold voltage levels.

Finally, we can back to the original circuit:

enter image description here

As you can see we add an RC circuit. So, now the capacitor can be charge/discharge via the R resistor from the op-amp output.

At beginning when the capacitor is discharged (\$0V\$ across the capacitor) the comparator output will be at \$+9V\$. And capacitor begins to charge via R resistor from the op-amp output. As the voltage across the capacitor rises the voltage at comparator input also. Once the capacitor voltage reaches the comparator upper threshold point (\$6V\$). The comparator will switch his output form high state (\$9V\$) to the low state (\$0V\$). And previously charged capacitor begins the discharge phase via resistor R into the opamp output. During the discharge phase the capacitor and the comparator input voltage decrease. But as sune as the capacitor voltage drops below the comparator lower threshold point (\$3V\$). Comparator output changes his state again from low to high and this stops the discharge phase and begins the charge phase. Therefore the capacitor voltage will swing back and forth between \$6V\$ and \$3V\$ forever as comparator output changes from low to high. As is was shown here (Fig. 4.2.3 and Fig. 4.2.4) http://www.learnabout-electronics.org/Oscillators/osc42.php

G36
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  • Thank you very much for the really detailed and clear answer. You couldn't have given a better explanation than this. Cleared all my doubts regarding this question. –  Nov 03 '19 at 16:21