8

schematic

simulate this circuit – Schematic created using CircuitLab

This is a simplified example of a push pull GPIO found in most microprocessors, with a load attached.

Using the capacitance and current values from the datasheet that is usually given in a microprocessor datasheet, how can the rise time be calculated?

Voltage Spike
  • 75,799
  • 36
  • 80
  • 208
  • I noticed there was not a good question about calculating rise times, so I created one. I'll answer it if no one else does. – Voltage Spike Oct 09 '19 at 16:56
  • What do R1 and C1 represent? – Huisman Oct 09 '19 at 16:57
  • GPIO capacitance, and line resistance (which is most of the time negligible) – Voltage Spike Oct 09 '19 at 17:01
  • 2
    Nice idea but, to make it worthwhile for that, you need to fill the question out a lot more before thinking about the answer. Guide new posters through what a decent question should look like. – TonyM Oct 09 '19 at 17:01
  • You also neglect Rdson? – Huisman Oct 09 '19 at 17:02
  • trivially, for a FET driving a capacitor, the speed will be gm/C. – analogsystemsrf Oct 09 '19 at 17:11
  • Are you designing the GPIO port at the transistor level or do you want to use a commercially available device? If the latter, then please provide a link to the device's datasheet. If the former, then please provide information about the transistor parameters. Are we concerned with short-channel effects? – Elliot Alderson Oct 09 '19 at 17:46
  • This is not an answer how to calculate it, but some datasheets like for example STM32 datasheets contain those values because these microcontrollers can have fast interfaces like RMII where the values are important, but some others like AVR datasheets don't contain the values. For STM32 these are defined multiple ways, like at which supply voltage and with what capacitive load and IO pin drive strength can a certain rise/fall speed achieved between which high and low voltages. Another way how they define it is that they state maximum square wave frequency achievable into given load. – Justme Oct 09 '19 at 18:28
  • 3
    [What is the output transition rate for a logic device?](https://e2e.ti.com/support/logic/f/151/t/718814) – CL. Oct 09 '19 at 18:42
  • @CL. Yep, that, incorporated with the load to find the fastest transition time for both port and load. – Voltage Spike Oct 09 '19 at 20:21
  • The MOSFETs transition between saturation and ohmic regions during the switching and there usually isn't a lot of information about the former region in a digital chip datasheet. You can make estimates, but it depends whether you're concerned about it switching too slowly or too fast (eg. for EMI considerations). You should add "maximum" or "minimum" times to the question. – Spehro Pefhany Oct 10 '19 at 00:00
  • _"Using the capacitance and current values from the datasheet that is usually given in a microprocessor datasheet, how can the rise time be calculated?"_ the same way you would calculate it in any other circuit with current and capacitance. But many MCU data sheets do not provide this information. – Bruce Abbott Oct 10 '19 at 03:54

1 Answers1

1

For this, and if you have access to it, you should better use IBIS models for the I/O cell.

The IBIS model not only provide for rise time and fall time modelling but also includes ESD diodes modelling which will make your simulations much more accurate (see Fig 9. for diagram).

matt__chv
  • 144
  • 7
  • Thanks but I'm looking for more of a hand calculation, IBIS models require expensive software. – Voltage Spike Nov 05 '19 at 22:40
  • Unfortunately, this sort of data usually isn't available for hand calculations. Something like a [IBIS -> SPICE converter](http://www.spisim.com/products/free-apps/spisim_ibis-a-free-web-app-for-simulating-ibis-using-free-simulators/) might help, but still wouldn't give you hand calculations. – user2943160 Nov 29 '19 at 21:57