Diamond: Warning: logical net has no load

Question

I've a Diamond project with 1 System Verilog module (using Synplify Pro for synthesis) with the code as follows:

module arrtest(clk, led);
input clk;
output reg led = 0;

reg [3:0] arr_index = 0;
reg [7:0] intervals [0:9]  = {8'd125, 8'd128, 8'd200, 8'd210, 8'd192, 8'd192, 8'd185, 8'd100, 8'd255, 8'd80};
reg [7:0] countdown = 0;

reg initialized = 0;

always @(posedge clk)
begin   
      countdown <= countdown - 8'd1;

      if(countdown == 0)
      begin
          countdown <= intervals[arr_index];
          arr_index <= (arr_index < 3'd10) ? arr_index + 4'd1 : 4'd0;
          led <= !led;
      end   
end

endmodule

And I've receiving the following warnings at the Translate Design stage:

Running DRC...

WARNING - logical net 'countdown_cry_0_S0[0]' has no load.
WARNING - logical net 'countdown_s_0_S1[7]' has no load.
WARNING - logical net 'countdown_s_0_COUT[7]' has no load.
WARNING - DRC complete with 3 warnings.

So I'm suspecting that something's wrong in the design and a part of the design doesn't get synthesized.

On the other hand on the Map Trace stage it gives me the following:

Top 10 highest fanout non-clock nets:
Net arr_index[0]: 12 loads
Net arr_index[1]: 12 loads
Net arr_index[2]: 12 loads
Net arr_index[3]: 8 loads
Net countdown6_i: 8 loads
Net countdown: 4 loads
Net countdown[4]: 3 loads
Net countdown[5]: 3 loads
Net countdown6_3: 2 loads
Net countdown6_4: 2 loads

And I'm reading it as "the countdown net IS loaded".

Why am I getting these "has no load" warnings and do they mean that a part of the design doesn't get synthesized?

If you haven't errored out completely, go into the schematic editor and look at what is not connected. The "_cry_0_sxxx" doesn't look like it comes from your code, but rather from the synth algorithm, probably because it used fixed bit width data type to implement your code, and now you've got leftover bits not being used (ie, not loaded). Incidentally, I've found that the Lattice LSE does a far better job than Synplify Pro for synthesis and place & route. — Bort, Sep 18 '19 at 20:41
@chadjo, Thanks. Will try with Lattice LSE (this is a sample design, I've another more complex one with similar warnings), the only thing that stopped me from using Lattice LSE was that one has to use verilog and it doesn't support unpacked arrays apparently, so I'll need to figure out a substitute `for reg [7:0] intervals [0:9]` — axk, Sep 18 '19 at 20:45

score 4 · Accepted Answer · answered Sep 18 '19 at 20:31

This is a pet peeve of mine with synthesis tools in general — they tend to spew out a lot of irrelevant warning messages that make it very difficult to find the real errors in a design.

In this case, it seems that the tool has recognized that your countdown variable is a counter, and used a general-purpose counter macro to implement it. However, this general-purpose macro has outputs that you don't need — and have no reason to know about in the first place. But the DRC cheerfully puts out warnings related to those outputs that mean nothing in the context of your actual design.

Short answer: These particular warnings are safe to ignore, but you can't generalize from that.

Diamond: Warning: logical net has no load

1 Answers1