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I realise that in all my circuits I consider active-high the "natural" default and active-low a goofy situation that needs to be inverted. I pull down all data and control lines (resets, output enable, input enable, inputs for an ALU or adder...), put inverters all over the place, and generally experience a lot of annoyance over every active-low pin.

Can you enlighten my what the advantages of an active-low architecture might be, or why I shouldn't care? It seems that wildly mixing avtive-high and active-low, based on the ICs demands, can be a nightmare to interpret, document and debug.

Zsolt
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Active low does have one significant advantage: the active level is always the same, even in systems where components run on different supply voltages or can be turned off completely (power gating). So for something like a reset line, it can make a lot of sense as you can hold components in reset while the power supplies settle and what not by simply pulling to to ground, which is usually the same voltage level for all components in a circuit. Presence detect pins also make sense to be active low - the device or connector only needs to short the pin to a ground pin, there are no dependencies on power supplies so there are no issues with sequencing or gating. Active low can also give an indication of a missing transmitter or bad connection, as in the case of most UARTs.

Anther consideration is the reset state of a pin. For example, it's rather common for FPGAs to have internal weak pull-ups active on all IO pins before they are configured. Therefore, it may make sense to make some external signals active low so they are not considered asserted before the FPGA is configured. Or maybe you want the signal asserted, in which case make it active high.

On the other hand, inside of a CMOS circuit, the logic level in most cases doesn't really make much difference. Long wires can be split by periodically inserting inverters, and you just need to make sure an even number are added or the inversion is taken into account by changing the destination logic. Additionally, it's common to build "inverted" versions of basic blocks such as full adders so you can chain adder with inverted outputs to adder with inverted inputs and reduce the number of transistors you need (this is because the core of a full adder is inverting, so a "normal" full adder includes at least one inverter). In many cases, the tools can do this automatically as an optimization step.

alex.forencich
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  • Thanks! Reset line is a tough example though, as an active-low reset line (more or less) acts as an active-high enable line, it's just the naming that makes it look active-low. – Zsolt Sep 02 '19 at 11:08
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    @Zsolt Szilagy: no, reset is a **perfect** example because: Reset needs to be active especially during power up when power supply (upper rail) is not yet stable and may be still different for different parts of the circuit. An active high signal could be quite error prone during that phase. It really is not "just the naming". – Curd Sep 02 '19 at 12:01
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    Enable and reset are totally different. Enable is usually a "hold" or "stall" input - maintain internal state, but ignore inputs/don't generate output. Reset is throw out all internal state and go back to a known initial state. – alex.forencich Sep 02 '19 at 12:24
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Active low signals were very often used in TTL circuits for noise immunity (apart from the drive capability as mentioned by Neil_UK).

The input of a TTL gate is guaranteed to recognise any level of 0.8V or lower as a low, and any input of 2V or higher as a high.

If the signal is taken true for only a short time relative to the false state (common in many memory systems) then the idle state (false) will have Vcc - 2V of noise immunity if the signal is active low (which was 3V in 5V circuits, 1.3V in 3.3V circuits) as opposed to 0.8V of immunity in the low state.

This assumes that the idle state is at the rails (a reasonable assumption for a single gate load).

So idling in the high state gave better noise immunity and this remains true for devices that have 'TTL compatible' inputs.

For the situation where the logic is difficult to understand, I suggest using assertion level logic notation which then makes the intent of the circuit quite clear.

Peter Smith
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In the bad old days of TTL, with its strong sink capability and weak source capability, and open collector being commonly used to OR signals, active low was a natural.

These days, with CMOS having more or less symmetrical drive capacity, it makes sense to use whichever you find easier to handle. I personally can do logic sums in my head more easily in active high than active low.

Some ICs will have active low inputs or outputs. Then it makes sense to 'ride the horse in the direction it's going'.

Neil_UK
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Others have mentioned the skewed output drive strength of old TTL bipolar logic gates, where pulling current down to ground is stronger than supplying current pulling up to Vcc.
For high-speed CMOS, drive strength is better-balanced: pull-up is nearly as strong as pull-down.

For 74HC04 basic inverter, pull-down is marginally stronger than pull-up. This trend often persists for other complementary-MOS gates and processors.
No big difference but every little bit can help....take for example driving a blue LED with a microcontroller I/O pin (running from a +3.6V supply). This is a marginal design where LED series resistance is small. I'd choose pull-down for that little bit extra headroom.

Another point favours pull-down. Good designers have a nag in their head whispering "ground integrity". So ground is almost always more solidly established than DC supply in a complex system. Where logic levels must have good noise immunity, pull-down is preferred. Bus distribution is most often ground-referenced for example.

glen_geek
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