Can someone explain me the terms : DRAM Rank and a DRAM Channel is simple terms.
I went through this PDF and I was not able to understand the DRAM Organisation/architecture on page 3 and page 11. Can someone help me understand those block diagrams.
I have seen some server board PCBs. In that, I have seen many DIMM Slots. Like, I have 12 DIMM Sockets. 6 sockets were black in color and 6 were blue in color. Does this difference indicate different channels, if not, why is there a difference?
You probably missed the concept of hierarchy.
Look at page 5: "DIMM, rank, bank, array form a hierarchy in the storage organization".
1 DIMM can have more than 1 ranks. One rank can have more than 1 banks, and so on. Some are vertical elements, some are horizontal elements.
Consider memory is organized cells, each cell a bit (value 0 or 1), and multiple cells in array; so to read the value stored in one of those cells (or to store a value in a cell), you must provide a "row * column" cell address. Because there are limits to the number of rows and columns, as well as efficiency problems when the array is too big, the hierarchy depth has been increased adding more dimensions. So instead of having just rows and columns... you have rows, columns, banks, and ranks. A full address to find the value in a cell would be: "row * column * bank * rank".
Let's make an example: you have a 32 bit DRAM controller. One bit is needed to say if the number is negative or positive; so you have 31 bits left for the numbers, this means that the biggest number it can use in one cycle is 2^31 (2,147,483,647). To use bigger numbers it must wait 2 cycles (the access time doubles! And the computer would halve its speed; and this would be unacceptable). A cell address is a number as well, and this means that the highest cell address is 2,147,483,647. In other words, if you had a simple row of cells, you would not be able to address more than 2,147,483,647 bits (i.e. : less than 256MB!). So instead of having a simple row of cells, they used an array: "rows * columns". This means that you can have "2,147,483,647 * 2,147,483,647" cells (trillions of bits can be addressed). If you add more depth to the hierarchy, you can get more addresses for cells.
This is an over simplified example. The real thing is much different. But I wanted to show you one of the advantages of increasing the heiarchy depth: increased address space.
Another advantage is the speed, because of parallelism. So, let's say that your cpu can read 2 values in 1 cycle. But your ram chip is organized in rows and columns, and to read one cell it needs to turn on (ie: give electricity) to 1 full row and 1 full column only, so that at the crossing of that row and column, a single cell turns on ... and allows you to access its value. How are you going to concurrently access 2 cells that are on totally different rows and columns, if you can turn on only 1 row and 1 column at once? One of those hierarchy levels could be used for this purpose, instead of using it to increase the address space. And here we go: channels. If you place data on different DIMMs, connected to 2 different channels, you can use both DIMMs at the same time, independently from one another. In this way your CPU can access both DIMMs at the same time, and get 2 values in 1 cycle.
To conclude: memory is organized in a multi dimensional matrix so that it is possible to work around all the limits (bandwidth, address size, electric needs, and so on) without compromising on performance. If you go back to your slides, you'll see that ranks, banks, arrays... are just unique names given to those dimensions.
Colors on DIMM slots can be anything. Can be the channel, but can be something totally different, example: some boards can have both DDR3 and DDR4, and because those two families have different voltages... you'd better not place the lower voltage one into a higher voltage slot, or magic smoke will puff your eyes. This doesn't happen nowadays, because every ram generation has a different number of pins and/or notch positions. But some bad DIMM/slot combos can still hurt your wallet... so pay attention anyway.
A DRAM Rank is a set of memories associated with a Channel (controller) that share a common address and data connection. Multiple Ranks can be connected to a Channel, but only one Rank can be activated at a time.
For example, if you have a 64-bit controller with two 64-bit DIMM slots, each slot is a separate rank. Only one DIMM is active at a time.
It is also possible to have multiple Ranks on a single DIMM. Nevertheless the principle is the same: one or more groups of physical chips, activated one group at a time.
A DRAM Channel is a controller interface that can talk to one or more Ranks. It is a common group of address / data lines that function together.
On devices have more than one DRAM Channel, the Channels can be treated either as separate address spaces, or aggregated together to create a wider interface.
When the Channels are aggregated together as a wider interface, the memories on each Channel must be the same size and type. If they are treated as separate spaces, there is more flexibility in how the memories are configured.
