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I'm studying this circuit:

enter image description here

The author of my book says that the purpose of this circuit, called "Self Biased Current Reference", is to generate a current almost independently of the supply voltage. He also says that, if M3 and M4 are perfectly equal, than I1=Iref. Then it follows that:

enter image description here

from which I can find VGS1 and I1.

Question 1: When the author says that the current mirror is perfectly matched and then I1=Iref, isn't it too much simplified? He neglects channel lenght modulation, but in reality the source-to-drain voltages of M3 and M4 will not be equal (because we have just M1 under M3, instead we have M2 and a resistor under M4)

Question 2: Why is this current almost independent of VDD? The author says:

"The value of the generated current weakly depends on the supply voltage because there is a high impedance element per branch capable of absorbing possible supply variations. These two elements are the transistors M2 and M3. The drain to source voltage of M1 and M4 can not change freely: the former is two VGS above ground the latter is one VGS below VDD. Any supply fluctuation is then “absorbed” by the high resistance that we have between drain and source of M2 and M3"

I don't understand the strong part of the text: why is any fluctuation “absorbed” by the high resistance that we have between drain and source of M2 and M3?

Thank you

Stefanino
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3 Answers3

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1) Yes, channel length modulation must be ignored to get the \$I_1 = I_{Ref}\$ relationship. Otherwise, as you correctly point out, the currents will depend on the voltage dropped across the remainder of the two branches of the circuit.

Channel length modulation can only be ignored if the transistors stay in saturation. If not, the drain current will depend on the drain-source voltage. But as long as \$V_{dd}\$ is high enough and \$I_{Ref}\$ is low enough, the drain-source voltage and consequently the gate source voltage (due to the gate-drain tie) will be high enough to keep the transistors in saturation and the mirror function intact.

2) While the mirror function is due to M3 and M4, the constant current source function is due to M1 and M2. As the equations indicate, the current is dictated by the relatively constant \$V_{Th}\$ and \$R\$. So how is the current kept constant, even as \$V_{DD}\$ varies?

As \$V_{DD}\$ rises, something must "take up" the excess voltage. The author uses "absorb" instead of "take up", which is fair because as well as providing the additional voltage drop, the extra power must also be absorbed, but it's the increase in voltage drop that is important here. M1 and M2 cannot perform this function, because as stated their drain to source voltage is relatively fixed, so it is up to M2 and M3.

Since the current mirror is enforcing \$I_1 = I_{Ref}\$, and the current source is enforcing constant \$I_{Ref}\$, additional voltage due to \$V_{DD}\$ is dropped over the drain to source of M2 and M3. This will remain intact while ever M2 and M3 can continue to produce large enough drain to source voltages. MOSFETs are capable of producing high drain to source "resistance", so the circuit can be made stable.

Heath Raftery
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  • Thank you for your answer. If we had to formally prove the independence of the current from Vdd, we should perform a small signal analysis. But by intuition, we can say that the variation of Vdd is absorbed by the high resistance that we have looking into the drain of M3 and M2, thus small signal current i is just the ratio between the small signal voltage and this high resistance (thus i is very small and dc current doesn't change too much). I don't understand why VGS is relatively fixed and why we consider (for example for the left branch) only rds3 and not the parallel of rds3 with rds1 – Stefanino Aug 25 '19 at 21:18
  • Another question: why do we need M2? The working principles of this circuit are 1) to impose VGS1 across resistor R and 2) to have I1=Iref. Then only a current mirror, one transistor (M1) and one resistor (R) are just required. Why then the presence of M2? Thank you – Stefanino Aug 25 '19 at 21:31
  • All good questions, and worthy of in-depth attention which the comment function isn't really suited for. I think your second question is easier - to keep Vds1 relatively stable (at 2x Vgs). But a complete explanation is probably difficult to achieve in this format. – Heath Raftery Aug 26 '19 at 01:18
  • I think to have understood: from an intuitive point of view (more rigorous approach should involve small signal analysis) we can assume that the drains of M1 and M4 are relatively fixed (because the gate to source voltage of a mosfet is "strong"), then these two drains behave more or less as a ground for the signal. Thus a (small) variation of Vdd can be absorbed only by rds2 and rds3, which are relatively large. As a consequence, for each branch, small signal current i=v/rds will be small, thus dc currents I1 and Iref will not change too much. Is it correct? Thank you – Stefanino Aug 27 '19 at 12:00
  • Sounds like a reasonable intuition. It's a pretty complex circuit to understand all at once, so that big picture assessment is probably a good way to tackle it. As you say, you can always zoom in and do small signal analysis and the like to get at the details. – Heath Raftery Aug 27 '19 at 20:15
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The current mirror, as configured, is not highly compliant to power supply variation. A cascode mirror would greatly improve performance, but would add another DS voltage drop.

I ran a simulation, and it is well worth while.

patellar-myotatic
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Note this circuit (like many self-biased circuits) also has a possible state with all currents (nearly) zero. If the V on the gate of M2 is 0, then it will be off. There V across R is then 0, and so M1 is also off. When M2 is off, its drain current is 0, so M4's current is also 0 and it is off. M3 is therefore off. This leaves the gate of M2 'floating' (undefined), and it can settle at any V between 0 and VDD. If it settles at a low value, M2 will remain off, and the circuit won't have started.

jp314
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