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I'm a bit confused about the pin spacings of SO8/SOP8.

Example: in Detail 2.54 SOP8, pin spacing is 2.54mm.

However, according to Small_Outline_Integrated_Circuit, fragment:

Small-outline package (SOP) After SOIC came a family of smaller form factors, small-outline package (SOP), with pin spacings less than 1.27 mm:

This seems to contradict each other.

So is SOP8 2.54mm, 1.27mm or less than 1.27mm? Or can it be anything? And SOIC8 always has a larger pin scaling than SOP8 (1.27mm, versus < 1.27mm)?

Or is there a standard and a lot of (especially Chinese) manufacturs do not follow them? And what about the Toshiba example?

Michel Keijzers
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2 Answers2

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You are correct that SOIC (as defined by JEDEC / IPC7351B) has 1.27mm pitch contacts.

SOP, TSOP, SSOP and TSSOP are expected to have a smaller pin pitch, but there is no actual standard that requires it.

The JEDEC definition of SOP.

Some packages do meet certain JEDEC registered packages, but as you can see from the screenshot, I am free to define a SOP / TSOP package with 2.54mm pitch pins if I choose to do so. It will simply be unlikely to have a JEDEC package standard associated with it.

IPC Compliant footprint wizard

Some vendors simply define their own package and reference their internal drawing in the datasheet - this is common with Analog Devices (and Linear Technology which is now part of AD).

Peter Smith
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  • I was already afraid of something like this (that the standard is not so 'standard'), but at leas I know I should search for SOIC instead of SOP to be sure if I want 1.27mm pin spacings. – Michel Keijzers Aug 20 '19 at 10:04
  • Each MFG will generally publish a package spec for their products and suggested footprint, it is generally difficult but not impossible to maintain generic footprints (KiCAD library team makes a encouraging attempt), but it is also common to simply make a footprint per each MFG spec. For quality assurance it may even be preferred to have footprint per part number as things are tweaked for specific purposes. Sometimes MFG will point to JEDEC in their package spec. – crasic Aug 20 '19 at 18:27
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That toshiba 2.54mm SOP8 is definitely a weird example, but I think it's fundamentally a JEDEC MS012 (SOIC 16 Narrow) with a custom leadframe that omits pins 2, 4, 6, 8, 9, 11, 13, 15, and has a slightly smaller body. If you sit this part on a standard SOIC 16 footprint, I bet it fits right in. I've seen optocouplers with this kind of arrangement. All IC vendors I have ever encountered publish their own package drawings, often incorporating references to JEDEC standards where possible. This is essential because the manufacturer is responsible for the actual leadframe and epoxy molding designs. If you compare package drawings from multiple vendors you'll notice minor variations, sub-mm. Usually packaging advancements are not driven by JEDEC, but are standardized only after the first or second manufacturer gets some successful design wins with the new package.

Over the years I've learned the hard way to always look at the package drawings, especially the lead pitch and body width. The early days of surface-mount packaging had "Small Outline" in both 0.150 inch and 0.300 inch, since 0.300 inch was the standard for narrow DIP. Sometimes when repackaging an IC for an SO package, the die size is too large to fit into the 0.150 inch "SO Narrow" package, so the "SO Wide" was used. It took awhile for the naming to get sorted out, so many older datasheets are very loose about what "SO" means. Same kind of thing happened with the move to SSOP, there was initial uncertainty about which lead pitch would win, so there are 0.65mm and 0.5mm, and even some 0.8mm SSOP out there -- not many, but just enough to cause trouble.

MarkU
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  • This for the insight ... and yes, I have likely the problem with 6N137 SMD optocouplers I ordered and which I'm now almost sure they will be too wide. So for now I will use the 6N137 DIP packages, those are reliable regarding pin spacing. – Michel Keijzers Aug 20 '19 at 10:38