Can anyone explain to me what is the logic behind high side RS flip flop, pulse generator, pulse filter from IR2101 internal structure picture ? The input circuit is easy to understand and also the low side circuit.
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The path thru the lower OR gate is DC_coupled.
The purpose of the various modules in the upper path is to produce behavior that appears as DC_coupled, but also achieves level translation, with low propagation delay, that draws low standby or quiescent current.
Accordingly
----- logic changes from the upper OR gate are differentiated in the "pulse generator" and converted into 50? nanosecond pulses;
----- the narrow pulse will turnon one of the FET/resistor level-translators, and the "pulse filter" (possibly AC_coupled thru a high-voltage on-chip capacitor) validates the incoming level-translated pulse, and then generates another pulse to control the Set_Reset latch
For really high voltages, the pulses travel thru Fiber Optic pathways.

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