I know FPGA design using VHDL and I came up some new topic recently that usage of triplication in FPGA but I am not confident about its understanding.
How can we use triplication in FPGA design and how do we verify this.
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2i don"t know what it is either, but why do you need to use it if you don't know what it is? – jsotola May 31 '19 at 06:22
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This is the enhancement to the current design strategy. – srihari May 31 '19 at 06:50
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2@srihari we'll need more context. "Triplication" is an English word and means "to make everything be there three times". But it's not clear how this would apply to VHDL design; if you just put the same VHDL modules there three times and then combined the results, the synthesizer will just optimize away two of them, because that's what synthesizers do: analyze the logic of a circuit and reduce it to the correct minimal amount of logic elements necessary to produce the same result. – Marcus Müller May 31 '19 at 07:06
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1The Ramans did everything in threes... – htmlcoderexe May 31 '19 at 20:41
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Triplication means (as noted) to make 3 of everything.
It is used in space and safety critical designs, and data results are voted; a disagreement in the vote has to be designed such that the erroneous result circuit is reset. For this to work within a single device, partial reconfiguration in the FPGA is required.
The reason this is necessary in SRAM based FPGA devices is that they are susceptible to single event effects (such as SEUs) which can flip a configuration bit from 0 to 1 or vice versa and therefore changing the effective circuit.
SEUs are caused primarily by high energy free neutrons and cosmic radiation (in space applications) although the lead in SnPb solder (in particular those on BGA devices) can also emit alpha particles as some of the lead is \$Pb ^{210}\$ which decays via \$Bi^{210}\$ and \$Po^{210}\$ to \$Pb^{206}\$ (Uranium decay chain) which is the stable state for lead.
Flash based devices are immune to configuration state changes from free neutrons although they can be susceptible to X-Ray, and the data path can be protected by parity or ECC.
Configuration CRC readback is also available for newer devices.
The implementation is vendor specific; Xilinx has an excellent application note on the subject.
Adam Taylor has a how to guide.
Peter Smith
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1This is clear as per the SEU effect on the semiconductor chip but how do we design in code and how to verify triplicate modular redundancy.. – srihari May 31 '19 at 09:57
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There is no information on the verification information of triplicate modular redundancy. – srihari May 31 '19 at 11:08
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Flash based devices are also susceptible. SEE can affect a wide range of semi-conductor devices... 1000A IGBT's can experience SEB due to neutron's at altitude. The susceptability might not exist at the configuration BUT it does exist at flip-flops. If you do no design your system to cope with the event (ie safe state machines, PLL reconfigure, filter/control-loop hickups) higher system failures can and do occur – May 31 '19 at 16:13
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@JonRB : I was involved in a large amount of research into device susceptibility in safety critical avionics and within the atmosphere at least, flash based configuration is unaffected by free neutrons. The testing is done at the Lansce facility. – Peter Smith May 31 '19 at 16:20
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@PeterSmith coincidently I work in this area as well. I never said the configuration was susceptible (I actually said "might not" since nothing is 100% certain plus also a polite way to say "it isn't" to feed into the statement other aspects of a design will be ) but flip-flops and BRAM most certainly are susceptible as I stated. – May 31 '19 at 16:22
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Is it possible to drive the triplicated nets on the fpga using simulation tools. – srihari Jul 30 '19 at 06:29