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I have following scenario

I[n] = nth Data Input, where n=1 to N
W = bit width of I[n]
A[k] = output of a signed adder, where k = 1 to N-1

I want to use my signed adders in following way:

A[1] = I[1] + I[2]
A[2] = A[1] + I[3]
A[3] = A[2] + I[4]
...
A[N-1] = A[N-2]+I[N]

As we are doing signed addition, bit length of output of each signed adder should be 1+(bit length of data input to the adder)

Thus the bit widths of adder output A[n] should be follows

A[1] W+1
A[2] W+2
A[3] W+3
....
A[N-1] W+N-1

My question is if N is a generic parameter, is it possible to declare in VHDL an array of N std_logic_vector's with bit-widths as W+1, W+2, W+3,... W+N-1 ?

The simple workaround to the problem is to have bit-width of each A[n] to be equal to maximum required bit-width i.e. W+N-1. However, this would mean that on synthesis same maximum sized signed adders of same bit-width are generated for each pair of input, potentially wasting circuit area.

nurabha
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1 Answers1

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Use the maximum bit width for A[n], but assign only the required bits in your loop:

A(1)(W downto 0) <= resize(I(1), W+1) + I(2)
A(2)(W+1 downto 0) <= resize(A(1)(W downto 0), W+2) + I(3)
...

The unassigned bits will be removed by synthesis.

Jonathan Drolet
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