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I am using ADC1 channel1 of STM32F303 in Time triggered mode. TIM1 is used to generate update event and is used as trigger source for ADC1. Time Trigger comes at 1kHz. I want to verify the total conversion of ADC. In F3 reference manual, it is mentioned that the maximum ADC clock can be set to 72Mhz. ADC is set in Asyhchronous clock mode and PLL clock 72Mhz (RCC_ADC12PLLCLK_Div1) is configured.

  • Sample time: 7.5 cycles
  • Resolution: 12 bit

Calculated total conversion time: sample time + conversion time = 7.5cycles + 12.5cycles(for 12 bit) = 20 ADC clock cycles.

  1. For ADC asychronous clock = 72Mhz: ((1/72000000)*20cycles)= 0.2777 us Tried to verify the same in Oscilloscope: I am enabling a GPIO pin to high in Update interrupt,and the same GPIO pin is made low in ADC EOC (EOC flag check) interrupt. The On time of the GPIO pin : 1.48us;
  2. For ADC asychronous clock = 12Mhz: ((1/12000000)*20cycles)= 1.666 us But in the scope it shows as 2.08 us. For ADC clock 72Mhz Suggest how to verify the conversion time.?
rinky
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    It takes time for the code to execute to toggle the GPIO; what you see here is the conversion time plus the code execution time. – Peter Smith Apr 26 '19 at 15:36
  • Interrupt latency. You may get closer to the actual sampling time if you disable interrupts and poll the EOC flag in a tight loop. - We had a very similiar question here last year. Why don't people trust the specified cycle counts from the STM32s' datasheets anymore? – JimmyB Apr 26 '19 at 15:43
  • @JimmyB , thank you, its just to verify. I was working in ADC dual interleaved mode, to give delay between master and slave ADC.I tried to check the delay time set between master and slave. There I needed conversion time of each ADC. So first I tried to check Single ADC with trigger. – rinky Apr 26 '19 at 16:15

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