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I have a faulty forgein system using an OMAP5912 whith external SDRAM and NOR-Flash connected. I have JTAG access to the unit with an Segger J-Flash. Now i want to debug why it does not startup anymore. From the powerdraw it looks like it gets stuck somewhere after poweron. I can connect to it by JTAG and also i can HALT the CPU abd MMU, but i can do this only after poweron, where the system is already hung up and maybe some initialized watchdog timers do strange things...

Is there a way to poweron the OMAP in a way that it does not execute any code? So i had a chance to setup the JTAG connection and step through the microcode from bootaddress 0x0 on?

HeckMeck
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  • Reduce Clk to 2MHz? – Tony Stewart EE75 Mar 04 '19 at 06:19
  • Are you saying the system runs normally if you reset it via JTAG, but not from its own power-on reset? In that case, you need to focus on the differences between the two types of reset, and it isn't likely to be the code. Look at things like power supply sequencing and ramp-up times. Also verify the startup behavior of any external oscillators. – Dave Tweed Mar 04 '19 at 14:36
  • How should reducing the clock help? Currently it uses two external crystals, on woth 32 khz and another with 48 Mhz – HeckMeck Mar 05 '19 at 14:29
  • Maybe i mixed something up with the resets, so please clearify. There is a cold start, name it POWER_ON_RESET (POR) and a warm start, name it SYS_RESET. Both come from outside the chip and clear the JTAG connection, if it has one and also let the system start from address 0x0. What i look for it a way to issue an reset but to keep the jtag connection and the CPU in halt mode, to prevent it to run any software. – HeckMeck Mar 05 '19 at 14:33

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