What are the advantages of CMOS operational amplifiers vs bipolar in the same class?

Question

Is there something else than Rail-to-Rail output and possibly lower power consumption for low frequency applications? Or Rail-to-Rail is the main one?

Answer 1

CMOS generally have lower offset currents, but larger offset voltages. Power consumption increases with GBW, no matter the technology. CMOS has intrinsically worse noise compared to BJTs, but this varies to much across the different op-amps that one cannot judge the noise performance based on IC-technology alone. But CMOS tends to have higher voltage noise, and lower current noise.

Rail to rail output is a cool feature, but it comes with some trade-offs in linearity. (See The Art of Electronics, chapter 5.9) And these configurations also have significantly higher open-loop output impedance.

Further reading in Art of Electronics Chapters 4 and 5.

Answer 2

CMOS transistors have the valuable feature of Width/Length. Bipolars do not.

For long-channel CMOS transistors, the current is

Idrain = K/2 * W/L * (Vgs - Vt)^2 and this is often simplified to read

Idd = (K = Mobility * Cox)/2 * W/L * Vt^2 where Vt is the gate voltage beyond threshold.

The Mobility and Cox are process-dependent, so consider them as constants. We have

Idd = K/2 * W/L * Vt^2

and that Vt can be changed, by orders of magnitude. Idd and W and L are our Degrees of Freedom.

Large Vt allow the opamp to MEASURE OUTSIDE the rails.

Again, playing with Idd and Width and Length will allow the design of CMOS transistors with enormous Vt, which allow the OpAmp to measure, to operate, with Vin+ and Vin- that are outside the rails.

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Usually, to reach outside both rails, that is to handle below Ground and above the VDD (or below -VDD and above +VDD), the silicon designer uses TWO sets of input differential-pair transistors: Pchannels to reach down, and Nchannels to reach up. HOWEVER these two sets of inputs must be COMBINED, and that combining-effect can result in irksome DC and AC performances.