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Im studying mosfets switching characteristics and one thing I happen to come across is the concept of "cross conduction".I searched around the web and couldnt find answer to my question.Kindly read whole post.

In the image below, mosfet-1 is on, as the voltage is applied to motor M,for a brief period of time mosfet-2 drain-gate voltage suffers from a sudden voltage spike, which maybe high enough for mosfet-2 to turn on, which is not the behaviour we want.

enter image description here Voltage spike(Drain-Gate)at mosfet-2(when it is supposed to be off) enter image description here All of this is understood, but what I dont understand is "why" this happens? Q) Is it because of inductive load(motor), which may oppose current in initial stage thus effecting the drain-gate voltage of mosfet-2 for a short period of time? Q) what can be done to prevent this ? Q) Also at lower +Vdd voltages(like 12-24-volts) will this be a significant problem,practically ?

Im talking in context to H-bridges only. Thank you for your time!

calculusnoob
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  • Is that Drain-Gate voltage or Gate-Source voltage? – Edgar Brown Feb 23 '19 at 11:53
  • @EdgarBrown It is Drain-Gate voltage of Mosfet-2. – calculusnoob Feb 23 '19 at 12:20
  • @EdgarBrown it is drain-gate, which in turn charges gate-source and you can get paracitic turn-on. Dangerous –  Feb 23 '19 at 12:23
  • When you specify voltage node names, this univocally determine their polarity. Your description makes no sense WRT the unlabeled waveforms presented. Please label nodes, polarities, and waveforms accordingly. Also M1 is not simply “on” it is being “turned on”, otherwise a transient behavior would not happen. – Edgar Brown Feb 23 '19 at 12:31
  • @EdgarBrown I will take care of node names next time, thank you. – calculusnoob Feb 23 '19 at 12:39

1 Answers1

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If we look at an inverter leg

schematic

simulate this circuit – Schematic created using CircuitLab

And it is such that the top switch is controlled while the bottom switch has no gate-drive (or gate-source termination). When the top switch is turn-ON/OFF the source of the upper device will be dragged up/down with respect to the load and the supply rail.

Since the top source and the bottom drain are connected, the drain of the bottom switch will also move.

Now consider the small signal characteristics of such a device

schematic

simulate this circuit

The Cdg capacitance (the miller capacitance) will facilitate charge flow which can charge up the Cgs of the lower device. If this charge is enough to raise the gate voltage to Vth, then the lower FET can potentially start conducting resulting in a shoot-through.

This is why there should always be a gate termination resistor and also a low-impedance gate-drive to absorb such charge flow

  • Is such phenomenon also a problem when Supply rail for mosfets is low voltage, like 12volts or something, will it be enough for significant shoot-through voltage at 2nd mosfet? – calculusnoob Feb 23 '19 at 12:42
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    it's not so much the voltage, but the speed of the switching. a rail of 3v could cause a shoot-through if the dt is high enough to cause enough charge to flow –  Feb 23 '19 at 12:43
  • Note that although your explanation is correct and it very likely represents what is going on, it relies on assumptions that are not warranted by the question. The questioner insists that the spike is in Vdg not in Vgs (which makes no sense). He also says that M1 is on not being turned on. – Edgar Brown Feb 23 '19 at 12:45
  • if the source of the upper (drain of the lower) moves because of either the load OR the upper devices switch, then there will be a dv/dt across the lower device. The spike at Vdg and not Vgs doesn't make sense, but there are other concerns with the question –  Feb 23 '19 at 12:51
  • @EdgarBrown Well, I didnot insist that spike is in Vdg, what I meant was that charges initially flows from drain to gate capcitor but missed the point that that charge will develop at Cgs, which causes parasitic turn-on. – calculusnoob Feb 23 '19 at 12:52
  • @JonRB When talking about H-bridges, is the parasitic turn of mosfet-2 because of load ? What triggers this kind of parasitic effect at mosfet-2? – calculusnoob Feb 23 '19 at 12:56
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    It can be. The inductive load wants to maintain current flow and thus that node may be pulled high to forward bias the upper body diode to maintain current flow. This action produces a dv/dt, which if poor termination is present, can cause parasitic turn-on –  Feb 23 '19 at 12:59