Is it possible to use conditional statements to modify parameters at compile time in Verilog?

Question

This question explains how to use Verilog parameters to combine constants from different modules at compile time. I am wondering if it is also possible to use conditional statements to modify parameter values at compile time.

Specifically, if the calculated total of the parameter values exceeds some maxLength, I want the parameter to 'wrap around' maxLength and be left with the remainder instead.

Pseudo-code example:

module toplevel {
    defparam myPole.offset = 95;

    pole myPole();
}

module pole {
    parameter offset = 0; // default value, overwritten by 95

    localparam x = 1;
    localparam y = 2;
    localparam z = 3;
    localparam maxLength = 100;

    localparam transitionConst = x + y + z + offset; // total is 101, this works as expected

    if(transitionConst > maxLength){
        transitionConst = transistionConst - maxLength;
    } // transitionConst should wrap around 100, and be left with 1
}

I looked at compiler directive tutorials at asic-world.com and TestBench.in, but the only if statements they describe are ifdefs. So, I suspect that Verilog does not support generic compile-time conditional statements. Is there a different approach I could use to accomplish this?

(P.S. I've seen Verilog Q&A on both EE.SE as well as StackOverflow. Which is the more appropriate community?)

Whatever you do, do ***not*** use `defparam`. It is strongly discouraged and the standardization body would loved to drop it if they could. — Oldfart, Feb 20 '19 at 18:41
I think this community is more appropriate. Stackoverflow describes itself as "_Q&A for professional and enthusiast programmers_", which is more SW centric, whereas, while ASIC/FPGA _design_ **uses** SW to describe the HW, it isn't the same as writing SW in terms of OOP aspects. ASIC/FPGA SV verification space, on the other hand, is OOP, but because it is still "HW engineering", I think you would be hard-pressed to get much help on stackoverflow for SV, and more likely to get it here. I could be wrong, but I would come here first. — CapnJJ, Feb 20 '19 at 20:03

dave_59 · Accepted Answer · 2019-02-20T19:34:41.013

7

You can use the conditional operator condition ? true_expression : false_expression as long as everything within the expression is a parameter or literal constant.

localparam transitionConst = (transitionConst <=  maxLength) ? x + y + z + offset : transistionConst - maxLength;

You can also use functions to define parameters, as long as all the function inputs are parameters or constants as well.

edited Feb 20 '19 at 19:34

answered Feb 20 '19 at 19:14

dave_59

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That is also known as a Ternary operator/statement if you want additional information – Veskah Feb 20 '19 at 21:27

CapnJJ · Answer 2 · 2019-02-20T20:05:19.083

You can do it it in your script (e.g. makefile) at compile time using maxLength as an input to an if-then-else statement that assigns a parameter value. Then pass these values using whatever mechanism the simulator you are using requires for you to specify the value on the command line (-g for Questa). Thus, for Questa/Modelsim, you would build your command line adding -g <name>=<value> to your vsim command. Look at command line reference for the details.

Is it possible to use conditional statements to modify parameters at compile time in Verilog?

2 Answers2