I'm unable to understand which PLL type (1 or 2) is better suited for frequency tracking and why? Can anyone explain how that additional integrator in type 2 will affect tracking?
Thanks in advance!
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1*"that additional integrator"* What that additional integrator? Provide a diagram or other data. – Oldfart Feb 19 '19 at 19:42
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The type of a PLL is determined by the number of integrators in its loop. I’m talking about that type. – thebionicandroid Feb 20 '19 at 04:13
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There's a pretty good answer here, although it's at the bottom of the pile in points.
The short answer is that a type 1 PLL (i.e, phase detector feeding into the VCO) needs a phase error to drive the VCO off of its preferred frequency, while a type 2 PLL (i.e., a phase detector feeding a proportional-integral stage) will drive the phase error to zero, regardless of how much the VCO must be offset from it's preferred frequency.
TimWescott
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The answer you’ve linked talks about order, not type. I do know that they’re related-order is the degree of the characteristic polynomial/degree of the denominator of the closed loop transfer function. And type is the number of integrators in the loop which introduces a pole. Hence, order can never be less than type. – thebionicandroid Feb 20 '19 at 04:17
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But what I’m looking for is a feel for what that integrator does. Does it help pull in faster? Does it help in tracking? I’ve understood the point about a static phase error present in Type 1 PLLs (due to finite DC gain). I just want to understand what the extra integrator in the Type 2 PLL does. – thebionicandroid Feb 20 '19 at 04:17
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Type I Phase detectors (like XOR gates or balanced mixers) are the integral of frequency error per unit time.
The phase detector outputs charge Pump Up/ Down current pulse or other pulse types. This requires LP filtering which adds more phase shift with frequency error or integration making the loop 2nd order and tends to be unstable with overshoot if the VCO error is too high. This results in longer capture times that increase rapidly with an initial frequency error. It may not acquire "phase-lock" if the VCO range is too wide and the frequency error is too high resulting in insufficient DC error feedback.
The reason for this is that while you get negative feedback for half the cycle, you get positive feedback for the other half so the difference is small if the frequency error is near the bandwidth of the LPF.
The Type II frequency detectors use synchronous edge detection instead of mixing at 90deg or quadrature offsets. Thus it becomes a fast stable 1st order loop but more jitter.
Thus the PLL design must define VCO range, stability tolerance and jitter when locked before a suitable design can be done.
Tony Stewart EE75
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Now this is interesting. I was assuming the OP was talking about the loop type, not the phase detector type. The "type I", "type II" phase detector terminology is, I'm pretty sure, limited to xx4046 type phase-locked loops -- at least, when I was taught this stuff anything outside of a 4046 data sheet called them "XOR", "multiplying", "three-state", etc. – TimWescott Feb 19 '19 at 20:10
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I wasn’t talking about the phase detector type. Only the PLL type. But your comment is informative, so thanks for that! – thebionicandroid Feb 20 '19 at 04:21
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The PLL type is defined by this Phase/Freq detector type. There are lots of other implementions for Type 1's and 2's but 1=Phase 2 =Freq which does not imply the Loop order in Control Theory rather the reverse. It started with the CD4046 – Tony Stewart EE75 Feb 20 '19 at 05:10