Is it possible to make hierarchy of constants in System Verilog?

Question

Is it possible to make a synthesizable hierarchy of constants in System Verilog?

For example:

There is a board with FPGA and several peripheral ICs.
Each IC have some setting registers.
Each setting register has a number of parts.
And each part has some possible values.

Is it possible to get these values with some like this DEV.REG.PART.VAL (not a DEV_REG_PART_VAL)?

Structs are not so excellent for making this hierarchy because of names intersection.

For example, there is a USB IC and a stepper-motor IC on board. A USB IC has a register SPEED with possible values LOW, HIGH and FULL. Stepper-motor IC also has a register SPEED with values 1RPM, 10RPM and 100RPM.

I would like to use a hierarchy like folders in a file system where I can create two different folders with the same names. And it is valid for all cases except "two identical names in one parent folder" (even same names parent and child folders).

CapnJJ · Answer 1 · 2019-02-19T19:48:15.630

I don't really understand your question, but, parameters are used in System/verilog (synonomous with constants in VHDL). A question was just answered about them: How do I calculate constant values across several modules at compile time in Verilog?.

It is possible to reference hierarchy with "dot notation" in the Verification-space of SV (i.e. OOP)... not likely for synthesis (tool dependent, maybe).

And, I wouldn't recommend trying to synthesize structs... maybe "packed structs" will work, but, it is kind of esoteric in terms of "explicitly defined Hardware". (Just my opinion... there are lots of things you can do in any language, but it doesn't mean you should)

Do you have access to IEEE1800-xxxx? If not, there are lots of resources online, and you may find a copy of the Accellera version somewhere... looks like Accellera doesn't have it on their site anymore (Officially graduated to IEEE, I suppose)

score 0 · Accepted Answer · answered Feb 21 '19 at 06:02

I am surprised but it is possible:

struct {
  struct {
    struct {
      int VAL1 = 1;
      int VAL2 = 2;
      int VAL3 = 3;
    } PART;    
  } REG;
} DEV;

assign out_port = DEV.REG.PART.VAL1;

It is NOT working in Quartus Lite 17.1

But it works in ModelSim 18.1 and Lattice Diamond 3.10 (Synplify 2017.03).

Is it possible to make hierarchy of constants in System Verilog?

2 Answers2