Is there a way to define enumeration for certain signals after simulation?

Question

I have run some verilog simulations in questa simulator and while viewing the waveforms i see that it would have been easier for me to debug the signals had there been some enums defined for them (To look at strings instead of bit streams).

Is there a way i can add enum definition for signals without re-running the sims say for example using some do file or using a feature in simulator (If there exists a generic solution)

I'm not familiar with Questa, but in Cadence SimVision you could use the expression calculator and a whole bunch of conditional expressions to convert to a string (not an enum). Does Questa have some kind of expression evaluator? — Justin, Jan 11 '19 at 19:21

score 1 · Accepted Answer · answered Jan 11 '19 at 20:47

You want a user defined radix. For example

radix define States {
11'b00000000001 "IDLE",
11'b00000000010 "CTRL",
11'b00000000100 "WT_WD_1",
11'b00000001000 "WT_WD_2",
11'b00000010000 "WT_BLK_1",
11'b00000100000 "WT_BLK_2",
11'b00001000000 "WT_BLK_3",
11'b00010000000 "WT_BLK_4",
11'b00100000000 "WT_BLK_5",
11'b01000000000 "RD_WD_1",
11'b10000000000 "RD_WD_2",
11'bzzzzzzzzzzzz "UNCONNECTED",
11'bxxxxxxxxxxx "ERROR",
-default hex
}

And then you can apply the radix States to your signal for use in the waveform or any other place you might want to examine the signal.

score 0 · Answer 2 · answered Jan 11 '19 at 19:59

0

Search on "virtual signals" in the documentation. you can split/join signals into a bus and create names for the new bus. Then if you save the waveform, it will still be there when you load it next time.

answered Jan 11 '19 at 19:59

CapnJJ

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Is there a way to define enumeration for certain signals after simulation?

2 Answers2