Specify exact pin locations on FPGA

Question

I have an Altera Cyclone IV FPGA, and I use the Quartus II software as the compiler.

In the "PinPlanner" it is possible to specify groups of pins (e.g. data buses). For each group, an I/O bank and an I/O standard (e.g. LVDS) can be specified. Then, the fitter (place and route) provides specific "Fitter Locations", specifying a precise pin for each individual wire.

Is there a way to specify the precise pin locations before the fitter attempts to fit the pins within each bank for me? Can this be done in the Pin lanner?

score 5 · Accepted Answer · answered Sep 18 '12 at 12:51

There are two ways of specifying PIN assignment — you can either use PinPlanner or set_location_assignment to specify the PIN along with set_instance_assignment to specify the IO standard.

I recommend you read I/O Management documentation from Altera. But here are few examples:

These are location assignments for 1 GbE RGMII Ethernet Interface:

set_location_assignment PIN_D25 -to eth_tx_clk
set_location_assignment PIN_V6 -to eth_rx_clk
set_location_assignment PIN_D17 -to eth_rx_c
set_location_assignment PIN_G20 -to eth_tx_c
set_location_assignment PIN_M20 -to eth_reset_n
set_location_assignment PIN_E21 -to eth_rx_q[0]
set_location_assignment PIN_E24 -to eth_rx_q[1]
set_location_assignment PIN_E22 -to eth_rx_q[2]
set_location_assignment PIN_F24 -to eth_rx_q[3]
set_location_assignment PIN_J20 -to eth_tx_q[0]
set_location_assignment PIN_C25 -to eth_tx_q[1]
set_location_assignment PIN_G22 -to eth_tx_q[2]
set_location_assignment PIN_G21 -to eth_tx_q[3]

set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_c
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_c
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_q
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_reset_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_q

And here is an LVDS clock input to FPGA:

set_instance_assignment -name IO_STANDARD LVDS -to in_clk_100
set_location_assignment PIN_AJ19 -to in_clk_100
set_location_assignment PIN_AK19 -to "in_clk_100(n)"

Hope it helps. Good Luck!

Thanks. You give examples of using `set_location_assignment`, but how can this be done using the PinPlanner? — Randomblue, Sep 18 '12 at 16:02
@Randomblue: Have you seen the doc? In PinPlanner, there will be a grid of top-level ports with pin location, I/O standard, etc. Just click, select values from drop-down, and that's it. — , Sep 18 '12 at 16:26
Aha, well my problem is that there is no "Location" column, just a "Fitter location" column that is populated after the Fitter has been run. — Randomblue, Sep 18 '12 at 16:31
@Randomblue: Are you sure you are in Pin Planner? You should see something like this — http://idle-logic.com/wp-content/uploads/2011/12/PinPlanner.png There is no Fitter location, that sounds more like a place & route... — , Sep 18 '12 at 16:33

score 1 · Answer 2 · answered Sep 18 '12 at 12:28

I haven't worked with Altera, but in Xilinx you could manually specify pin assignments before the compile in the constraints file (.UCF for Xilinx).

From what I can tell, you can do the same thing for Altera in the Quartus II .QSF file by using set_location_assignment.

See the example .QSF file on page 6 in this Quartus II Handbook.

Specify exact pin locations on FPGA

2 Answers2