Controlled Traces Length in SD card

Question

I my new design I need to use SD card communication. I would like to match all the impedance traces and control the length of the traces. Regarding the controlled length, is there a rule of thumb to determine which can be the maximum difference between two uncoupled traces?

Answer 1

The speed of a signal in a PCB is about half the speed of light: 15cm/ns .

The maximum difference between two signals, or more precisely, between the clock signal and any other data signal depends on the timing specification. At all times the hold and setup times vs. the clock must be respected.

At 50MHz, a clock cycle is 20ns, which corresponds to a length of about 300cm. At 50MHz, the setup time is 6ns and the hold time is 2ns relative to the clock signal (according to a document about SDCards).

Changing the data output at the same time as the clock signal would make it difficult to respect the hold time without introducing a delay of 2ns on the data signals. Delaying the data signals with a 30cm trace length each will take up some space on your board. Changing the data output on the inactive edge of the clock leaves a margin of about 8ns (10ns - 2ns), which corresponds to 120cm. I would not expect to have that much difference in trace lengths.

So in practice it is unlikely that you have to care about the trace lengths for your SD Card.

For your information: a very long time ago a colleague of mine needed a delay of "exactly" 1ns. Following my proposal, that delay was added by drawing a 15cm line in a 1cm x 1cm square on the board. This was the first thing that my colleague measured when the board came back: he observed a delay of "exactly" 1ns. Which confirmed that the speed of the signal in the board is 15cm/ns. That can vary a bit of course depending on the electrical properties of the board, but it will be very close to that number.

Answer 2

SDIO interface, the data bus used for SD cards, has unidirectional clock. Meaning that the controller will always be the output for the clock signal and the card is the input. The other signals are bidirectional.

With this interface there is no need to match the trace lengths, because there will always be length mismatch when reading the card.

This is easy to prove.

Lets first assume some variables, I'm too lazy to check the actual values from MMC standard, but these should be in the correct ball park:

• Clock frequency: 50 MHz, Clock cycle length: 20 ns
• Output hold time: 10 ns (The time how long after a rising clock edge the data signals are switched)
• Input setup time: 3 ns (The time how long before the next rising clock edge the data must be stable at the receiver)
• Input hold time: 3 ns (The time how long after the next rising clock edge the data must be stable at the receiver)

Signal velocity is roughly 15 cm/ns. Lets also assume that the clock signal is 15 cm long, so its time of flight is 1 ns.

Lets see what happens when we are writing to the card:

• 0 ns, rising clock edge at the controller
• 1 ns, rising clock edge arrives to the card
• 10 ns, data signals at the controller are switched
• 18 ns, input setup time starts (3ns before rising clock at the card)
• 20 ns, rising clock edge at the controller
• 21 ns, rising clock edge arrives to the card, data is sampled.
• 24 ns, hold time ends (3ns after rising clock at the card)
• 27 ns, next data signals at the controller are switched

From this you can see that the maximum allowed time of flight for the data signal is 18 ns - 10 ns = 8 ns. Maximum trace lenght would be 120 cm.

Reading the card is more interesting.

• 0 ns, rising clock edge at the controller
• 1 ns, rising clock edge arrives to the card
• 11 ns, data signals at the card are switched
• 17 ns, input setup time starts (3ns before rising clock at the controller)
• 20 ns, rising clock edge at the controller, data is sampled.
• 21 ns, rising clock edge arrives to the card
• 23 ns, hold time ends (3ns after rising clock at the controller)
• 28 ns, next data signals at the card are switched

From this you can see that the maximum allowed time of flight for the data signal is 17 ns - 11 ns = 6 ns. Maximum trace lenght would be 90 cm. This is tighter than the limit when writing. But here you can see, that the clock kind of travels back and forth, while the data only travels to one direction. Thus even if the traces are exactly the same length, the clock signal is effectively twice longer. The actual limiting value is the maximum length for data and clock signals combined.