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First time in my life I'm using this DDS chip (AD9850) to create sine wave at a desired freq, where I upload the lookup table code and the desired freq. command via a with micro-controller. So my knowledge at the moment very limited.

The thing seems fine so far but the problem is at very low frequencies. At 1Hz and even 0.5Hz seems fine. But I also need down to 0.1Hz.

Here is the output of DDS when I send the number 0.1 to the DDS via the micro controller:

enter image description here

In my code I send the command from PC to micro as string and convert it to double. But for simplicity and to verify I use this code, and for 0.1Hz I set sendFrequency(0.1) in the loop.

But as you see the period is around 11.5 sec instead of 10 sec for 0.1Hz command.

I hope I could explain the issue well. Is there a way to calibrate or fine-tune this so that I would have more accurate result? Or I should live with the accuracy? Btw where in the data sheet one can refer to such relative uncertainty?

manassehkatz-Moving 2 Codidact
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floppy380
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    so, what's the control word you're sending to the DDS chip, and what's the reference clock you're using for the DDS chip? What did you expect to happen, and how far off are these 11.5 s from that? We'll need a lot more knowledge on your system! – Marcus Müller Nov 21 '18 at 13:26
  • @MarcusMüller I use this code http://softgeniedoc.dk/contents/projects/AD9850_tonegen/AD9850.html just abit modified but the core is the same. I couldnt infer what is the clock being used from the code. I provided the code and the chip what else you need more let me provide. – floppy380 Nov 21 '18 at 13:31
  • you wired up the chip to a reference clock. You're literally the only one in this world who can tell us what the reference clock is; the circuit is sitting in front of you, not of us! – Marcus Müller Nov 21 '18 at 13:37
  • Oh I see I thought it is fixed or changed by the code. I will measure and come back. – floppy380 Nov 21 '18 at 13:38
  • It is this module http://telecnatron.com/modules/ad9850/index.html so it seems 125MHz – floppy380 Nov 21 '18 at 13:40
  • The first paragraph of the data sheet you linked answers pretty much all of your questions. – David Schwartz Nov 21 '18 at 22:48

2 Answers2

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It's not an accuracy thing- it's resolution.

The front of the data sheet specifies tuning resolution of 0.0291Hz with a 125MHz clock.

\$0.0291 \approx \dfrac{125\times 10^{6}}{2^{32}}\$ Hz (since the phase accumulator is 32 bits)

So that's about 30% of your desired output frequency. That comes from the result of adding the LSB of the tuning word to the phase accumulator at 125MHz- for a given clock frequency, it's inherent to the chip and the number of bits they chose for the phase accumulator and tuning word.

You can try reducing the clock frequency- the minimum is 1MHz so you should be able to improve the resolution by more than two orders of magnitude, to around +/-0.23% at 0.1Hz.

\$0.23\times 10^{-3} \approx \dfrac{1\times 10^{6}}{2^{32}}\$ Hz resolution with a 1MHz clock

Unfortunately, other things are going to have to change for optimal performance (especially the output filter- which is typically a 7th order elliptical LC filter on these modules).

If you never need to go above, say, 1Hz, you can simply add an RC filter with a cutoff of, say, 100Hz to the existing output and it will be acceptable for many purposes.

Spehro Pefhany
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  • The code is very complicated. I dont even understand how they create sine wave in the code. But do you have an idea what in the code http://softgeniedoc.dk/contents/projects/AD9850_tonegen/AD9850.html if I cahnge I can change the clock freq? What divides the 125MHz freq. I mean – floppy380 Nov 21 '18 at 14:02
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    Nothing divides the 125MHz from what I can see (other than the DDS itself, of course). You would have to unsolder the oscillator and replace it with a different (lower) frequency module. Or disable it and apply an external clock (it may have an enable input..you can look it up). It's a hardware change. – Spehro Pefhany Nov 21 '18 at 14:04
  • I see , I thought the tuning word would divide the freq. – floppy380 Nov 21 '18 at 14:06
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    It does, of course, but they didn't put enough bits in there for your application. If they had added another 8 bits to the tune word and the phase accumulator you'd be happy (and people who don't need such low frequencies would have to pay slightly more and send more bits to tune the DDS so they wouldn't be as happy). – Spehro Pefhany Nov 21 '18 at 14:08
  • Does that mean this chip AD9850 does not have those bits? – floppy380 Nov 21 '18 at 14:09
  • Or you mean the module is not providing such pins ? – floppy380 Nov 21 '18 at 14:12
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    Correct. But it does accommodate as low as a 1MHz clock so all is not lost, even for your application. The module output filter (those inductors and capacitors and resistors) will not be appropriate though so the output will tend to be noisy with a much lower clock frequency. – Spehro Pefhany Nov 21 '18 at 14:12
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    Nothing to do with pins. But the module clock and output filter is designed for 125MHz fixed. – Spehro Pefhany Nov 21 '18 at 14:12
  • A DDS with more than 32-bit internal math would be a lot. This is basically a radio part, and probably not what you want for generating ultra low frequencies. If you can modify it for DC coupling a computer *sound card* might well work, driven by a software implementation of DDS. – Chris Stratton Nov 21 '18 at 14:14
  • @SpehroPefhany It seems one of the output has no filter check here https://2.bp.blogspot.com/-f28-j1b6mqU/UyXHhSdXL9I/AAAAAAAABLA/Ewrz4oEqlpA/s1600/c41y.jpg – floppy380 Nov 21 '18 at 14:20
  • @ChrisStratton A bench function gen can go down to 1mHz Im wondering what DDS chip they are using – floppy380 Nov 21 '18 at 14:25
  • Looks like a pretty substantial LC filter to me. It's a **7th order elliptical filter**. If you never need to go over, say, 1Hz just tack an RC filter with a 100Hz cutoff on the output, it really depends on your requirements. As to bench arbitrary function generators they would typically use an FPGA, fast RAM and DAC rather than a chip like that. – Spehro Pefhany Nov 21 '18 at 15:24
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    @SpehroPefhany -- lower end bench FGs can and do use premade DDS chips. Furthermore, ICs like the [AD9106](https://www.analog.com/en/products/ad9106.html#product-overview) can perform A/FG style (fixed-rate) arbitrary waveform generation. (The higher end ones would indeed use a FPGA + RAM and a separate DAC, but they're still the same basic thing at heart, just rolling their own implementation :) – ThreePhaseEel Nov 22 '18 at 00:29
  • @ThreePhaseEel Not sure about the lowest end ones, but the ca. $100 Chinese ones use an Altera Cyclone IV FPGA driving a 14-bit DAC (or a resistor DAC for the crummiest ones). – Spehro Pefhany Nov 22 '18 at 00:39
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    @SpehroPefhany -- interesting that they've basically rolled their own DDS in a FPGA then. Wouldn't surprise me if that was a price tradeoff as well, though -- dedicated DDS chips are not particularly cheap. – ThreePhaseEel Nov 22 '18 at 00:44
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What you're looking for on the datasheet is the frequency tuning resolution. For this chip it is 0.0291 Hz for a 125 MHz reference clock input. Your frequency will be rounded to a multiple of this number. This number is based on the frequency of the clock input of the chip.

For example, 0.1 Hz will be rounded to 0.0873 Hz (0.0291*3). The period for 0.0873 Hz is 11.5 seconds which is what you're seeing.

A lower input clock frequency will give higher accuracy at lower frequencies. So if you wanted better accuracy at lower frequencies then lower the clock frequency.

Pangus
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  • How do you calculate the output rounded freq.? For example if I send 0.5 to the chip can you show what formula used and what would be the output? So that i can predict for each – floppy380 Nov 21 '18 at 13:59
  • It rounds down to a multiple of 0.0291. To find closest multiples, divide 0.5 by 0.0291, round down to the nearest whole number and multiply by 0.0291. 0.5/0.0291 = 17.18 which we round to 17. Then 17*0.0291=0.4947. So if you input 0.5Hz you would actually see 0.4947Hz – Pangus Nov 21 '18 at 14:09
  • Oh nice I can even plot the error versus freq. now- – floppy380 Nov 21 '18 at 14:10
  • @ChrisStratton Oops. yeah you are right. I edited my answer. Thanks – Pangus Nov 21 '18 at 14:17
  • By the way how can I learn to output an arbitrary periodicoutput rather than a sine? In other words in what part of the code is creating the lookup table? Thanks – floppy380 Nov 21 '18 at 14:27
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    You can do frequency modulation and amplitude modulation but I don't think you can change the lookup table on the chip. If you are interested in making arbitrary waveforms then it might be worth looking into a different chip or getting a DAC and trying to create your own DDS – Pangus Nov 21 '18 at 14:45
  • Oh I thought the wave form is uploaded by the micro controller. It seems the sine wave is hard-coded on the chip memory according to what you say. – floppy380 Nov 21 '18 at 14:48