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I mean compared to ICs (ASICs) with similar complexity, speed etc. Let's compare Ethernet switches to Kintex FPGAs (note that the most expensive switch from the list is circa as expensive as the cheapest Kintex):

  • FPGAs are well structured ICs (like RAMs). They can be scaled and developed easily.
  • The design tools (Vivado, Quartus, etc.) are expensive too, so I think the price of an FPGA is the price of the IC (and development) itself excluding the cost of support and the tools. (Some non-FPGA vendors give free tools whose development cost includes the IC price.)

Are FPGAs produced in lower quantities than other ICs? Or is there any technological harness?

Peter Mortensen
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betontalpfa
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    I think someone have made Ph.D. thesis in business science on the subject. It is not tech question, it is more business question involving tech comparison of apples with oranges. The main rule is - development tools (products) are always more expensive than consumer products - for various reasons, from revenue/cost estimation, and market demand, and availability of competing (functional) products. – Anonymous Nov 07 '18 at 11:53
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    Have you ever looked into a high end FPGA and all the features it offers? It is far from trivial to make it all work well together and anticipate the possible interactions. A similarily complex ASIC is also expensive as hell in the same numbers, the point where ASICs become cheaper is when are sold in the many millions. And your comparison is quite unfair because ethernet switches generally do not contain nearly as much complexity as an FPGA with all the PLL and signal conditioning and thousands of GPIO pins. – PlasmaHH Nov 07 '18 at 11:58
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    I don't get the comparison. Fpga cost anywhere between 80 cents and 50000$ - depending on size and features. Ethernet switches start at 20 Dollar and go up at least to severl hundred thousand dollar, ahain depending on size and features. – asdfex Nov 07 '18 at 13:22
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    As someone that works with both FPGAs and ethernet switches: why are those your two datapoints? – DonFusili Nov 07 '18 at 13:33
  • All vendors offer a free tier of FPGA tools, and all of the paid versions are a fraction of the price you'd pay for a full ASIC suite like Synopsys. So a lot of the cost of developing tools are most definitely included in the price of the hardware. – user71659 Nov 08 '18 at 00:15
  • And if you're comparing cheap Ethernet switches, [Xilinx themselves](https://www.xilinx.com/publications/prod_mktg/pn2035.pdf) show implementation on a $50 low-end Spartan, not their mid-range Kintex line. Besides, high-end Ethernet switches are not available from Mouser, check Avnet. – user71659 Nov 08 '18 at 01:12
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    Sorry to be harsh but: "A chip that can do everything is more expensive than a chip that can do only 1 thing". How's that even a question? – Agent_L Nov 08 '18 at 09:23
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    I choose ETH switches because the price of an FPGA highly depends on the transceiver count and performance. And ETH switches has also several transceiver, however they're price is not rising as much. – betontalpfa Nov 08 '18 at 13:13
  • @DonFusili as someone who works with FPGA's and a few others... fpga's and ethernet switches can be comparable since the Igloo2 series of FPGA's were developed in partnership with Cisco for some of their higher end switches ;) –  Nov 08 '18 at 20:25
  • This is just basic engineering economics, fpgas do not have the volume needed to hit a lower price point. – copper.hat Nov 02 '20 at 22:54

4 Answers4

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FPGA chips include both logic and programmable connections between logic elements, while ASICs include only the logic.

You'd be amazed at how much chip area is devoted to the "connection fabric" in an FPGA — it's easily 90% or more of the chip. This means that FPGAs use at least 10× the chip area of an equivalent ASIC, and chip area is expensive!

It costs a certain amount to do all of the processing on a given silicon wafer, no matter how many individual chips are on it. Therefore, to a first approximation, the chip cost is directly proportional to its area. However, there are several factors that make it worse than that. First, larger chips mean that there are fewer usable sites on the wafer to begin with — wafers are round, chips are square, and a lot of area is lost around the edges. And defect densities tend to be constant across the wafer, which means that the probability of getting a chip without a defect (i.e., "yield") goes down with chip size.

Dave Tweed
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  • In a similar vein (not enough for an answer, I don't think) is the fact you can't use all the LUTs due to timing constraints, so you always have excess. Further, you will not be using the full capability of the all LUTs, as some will end up being a simple inverter etc. – awjlogan Nov 08 '18 at 00:44
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    Certainly an ASIC will need some level of internal connection. I think you mean the FPGA has a bunch of connectivity, wires and accompanying switches, going to places that you don't necessarily need, whereas ASICs are built with only the ones you need. – user71659 Nov 08 '18 at 01:03
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    FPGAs probably require more test time, and test time isn't cheap either. – Nick Alexeev Nov 08 '18 at 03:37
  • Regarding the "*and chip area is expensive!*", I've never understood this reason. Aren't wafers relatively cheap? – Harry Svensson Nov 08 '18 at 09:03
  • @HarrySvensson the wafers are relatively cheap, but the processing to turn them into ICs is expensive, especially the production of processing masks. So the larger the chip, the larger the masks (pricey), and the more wafers you need to process to get the same number of dies. – Tom Carpenter Nov 08 '18 at 09:10
  • @TomCarpenter That's not true - the mask is the size of the wafer, not the size of the chip. Masks are expensive when you go down in process size due to the difficulty in fabricating them. Bigger chips have lower yield as there is a higher probability of a defect in given chip on the wafer. – awjlogan Nov 08 '18 at 09:17
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    @awjlogan Not with modern huge wafers - AFAIK they use a ["step and repeat" process](https://en.wikipedia.org/wiki/Stepper). – Tom Carpenter Nov 08 '18 at 10:24
  • @TomCarpenter On reflection, I still don't think the mask size is the cost driver on area. It's the reduced yield, not the cost of the mask. I would *assume* that a fab has a (small set of?) standard mask size, which the customer then fills with _N_ of their design. The cost of the mask is thus independent of the actual size of the chip. Now, if you have to develop a new process for a huge single chip, the mask size would of course factor in but would still amortise, whereas yield problems would not. – awjlogan Nov 08 '18 at 10:43
  • @user71659: Yes, that's exactly what I said! An FPGA might be <10% logic and >90% connection fabric, while an ASIC will be more like >90% logic and <10% devoted to interconnect alone. If we assume the amount of logic is the same in both cases, that's a huge change in chip size. – Dave Tweed Nov 08 '18 at 11:48
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    @HarrySvensson: From the [Jargon File definition for **nanoacre**](http://www.catb.org/jargon/html/N/nanoacre.html): *"A unit (about 2 mm square) of real estate on a VLSI chip. The term gets its giggle value from the fact that VLSI nanoacres have costs in the same range as real acres once one figures in design and fabrication-setup costs."* This has been true for a very long time. – Dave Tweed Nov 08 '18 at 11:51
  • @awjlogan the process gasses used are very expensive, the silicon itself is expensive for modern wafer diameters, the equipment is also relatively expensive to run, The mask cost are NRE, not a unit processing cost. – crasic Nov 08 '18 at 17:42
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    All said and done the actual physical die coming out of a fab is really not that expensive, it always bothers me that a big IC tends to cost a fraction of the package they are being put in. Where area becomes really expensive is in yield. A wafer has defects, and ICs that are 100 to a wafer would be 10 times more likely to fail due to a defect than ICs that are 1000 to a wafer. Not to mention the extra expenses of testing and engineering that goes into them. An FPGA can be reticle-limited, that is the maximum size allowed by the technology, at >25mmx25mm while a common IC will be just ~4mm^2. – Edgar Brown Nov 08 '18 at 21:00
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Another key driver of cost is verification.

FPGAs need to be individually tested before sale. This is partly to ensure that all of the thousands to several million routing interconnects and logic cells are functional. The verification however also involves characterisation and speed grade binning - determining how fast the silicon can operate and that the speed and propagation delays of all the many interconnects and cells are suitably matched to the timing models for its grade.

For ASIC designs, testing is typically simpler - a yes-no does the design perform as expected. As such the time required for verification is likely far less, and thus cheaper to perform.

Tom Carpenter
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    ASICs are usually tested with a scan chain. I see no reason why this wouldn’t be possible for FPGAs. There are also ASICs which are individually calibrated and tested at different temperatures and they still sell for a couple of dollars. – Michael Nov 08 '18 at 12:48
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    With an ASIC, correct operation is already defined - with an FPGA, you need it operating correctly REGARDLESS of how that is (user) defined.... – rackandboneman Nov 08 '18 at 20:15
  • ASICS and other chips are all tested and, often, binned for speed. I would accept this as a valid argument if anyone could produce even rough numbers for how long an FPGA needs to sit on a test bench compared to other types of chips. My intuition is that, even if longer tests are needed, the rest of the manufacturing process is probably dominant in terms of contributions to production costs. To maintain throughput they may need a larger testing line to offset the longer individual test times, but it's such a small part of the produciton process that I remain sceptical... – J... Nov 12 '18 at 14:13
  • @rackandboneman Correct operation for an FPGA is also defined. They can test every logic element and interconnection separately. What you're saying would be like saying that CPUs can't be tested because they need to operate correctly regardless of what software runs on them. – user253751 Jan 14 '19 at 02:33
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There is one (more) important point which is usually overlooked, process technology.

FPGAs that have high market share are manufactured with cutting edge technology. To be more specific, Kintex-7 FPGAs have TSMC 28nm process and their shipment started in 2011[1]. TSMC had started mass production of 28nm in the same year[2].

[1] Xilinx ships first 28nm Kintex-7 FPGAs (By Clive Maxfield, 03.21.11)

[2] Chang said: "Our 28-nm entered volume production last year and contributed 2 percent of 4Q11's wafer revenue."

I don't know the process of the ethernet switches, but most of the ASIC design companies don't follow the cutting edge technology. It doesn't make sense for foundries as well.

The following chart shows TSMC's revenue by technology (1Q18). Even in 2018, 39% of the revenue comes from technologies older than 28nm. If we think about the number of chips, it is not hard to imagine that more than half of ASICs are today manufactured with technologies older than 7-year-old Kintex-7.

TSMC revenue by technology

As a conclusion, process technology is one of the factors that make FPGAs more expensive. I don't claim it is a dominant factor, but significant enough to be considered.

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I'm going to go out on a limb and say that this is by far dominated by simple supply and demand. Ethernet switches are mass produced with huge economies of scale and sell at discounts over chips that are not so widely used. FPGAs, I'd say, are not nearly so widely deployed as ethernet switches and so they cost more because the development and infrastructure costs are spread over fewer customers.

This isn't about process or die size or anything like that. Consider the Xilinx Virtex-7 (only because I could more readily find data for it) and let's compare to a few contemporaries :

  • Virtex7 (2011), 28nm, ~6.8 billion transistors, $2500USD (popular models) to $35,000USD (higher end models)
  • NVIDIA Kepler GK110 (2012), 28nm, ~7.1 billion transistors, Tesla K20 cards ~$3200USD at launch (chip price some smaller fraction of that)
  • XBoxOne SOC (2013), 28nm, ~5 billion transistors, $499 USD for whole XBox at launch
  • Xeon E5-2699 v3 [18 core] (2014), 22nm, ~5.6 billion transistors, ~$4500USD

So overall the Virtex FPGA seems reasonably priced (more popular models) compared to other silicon of a similar transistor count, generation, and sales volume. The XBox SOC sticks out as something which was widely deployed in a consumer device and the cost is likewise much lower.

NVIDIA's compute GK110 was much less widely deployed than similar consumer chips that ended up in gaming cards and was similarly more expensive, even given the architectural similarities and the fact that the chips were made in the same factory.

As for the Virtex chips, there isn't a 10x difference in the complexity of the $2500 chips vs the $35000 chips - the latter are simply much less popular and, with lower sales volumes, the cost per unit is necessarily higher.

The market is full of this. Anything you can sell a hundred million of you can always make cheaper than something you will maybe sell a hundred thousand of.

J...
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  • I don't think you can trust the $35,000 price from digikey or wherever to be an accurate representation of actual quantity pricing. Probably closer to $5k...at launch... – ks0ze Nov 09 '18 at 03:33
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    I'm not sure how true this is, but I was lead to believe that consoles such as the Xbox are typically sold at either a loss or at cost, and the difference is recouped through game sales. – Élie Nov 09 '18 at 04:38
  • @ks0ze, very few customers buy $35k chips in really large quantities (10k/month or more, say). And last time I needed to buy from Xilinx, they claimed to only sell through distribution (whether this is actually true when buying 1000s of units I don't know). – The Photon Nov 09 '18 at 04:56
  • That said, you certainly can call the distributor and negotiate a better price if you want more than a few 100 parts. – The Photon Nov 09 '18 at 04:58
  • @ks0ze That is the actual book price from Xilinx. If you want just a few, that's what you'll probably have to pay. Xilinx are hard cases with prices, but you can bargain down if you're buying a lot, yes. I don't think that tells us anything except that FPGAs aren't bought and sold in large enough quantities to have a highly stable price structure. Consider bulk discount margins you'd get on high volume products like Intel CPUs, for example. Maybe a few percent, but that price isn't moving a lot. Same with ethernet switches and XBoxes, which is the point of this whole answer. – J... Nov 09 '18 at 10:27
  • @J... you really don't need to buy all that many to get a significantly better price. Why do you think the list price for Xilinx (& 3rd party) dev boards with the exact same parts are a fraction of the "list price" of the part? For instance the Virtex Ultrascale+, the VCU118 eval kit it $6,995 on from Xilinx but the FPGA by itself is $45,000 on digikey. – ks0ze Nov 09 '18 at 17:27
  • @ks0ze Well dev boards are made by 3rd parties who are buying chips in bulk, so yeah, of course they can leverage discounts. The point is that a product where you can haggle away 80% margings off of the list price is, ipso facto, one which isn't a mass production part - the inelasticity of supply and demand that results (and the wild pricing schedules) is just a symptom of this. I'm not disagreeing that there is huge room to bargain - I'm using that fact as evidence that the market is both small and reasonably inelastic. – J... Nov 09 '18 at 17:32
  • @J... I guess I would argue that the Tesla K20s are equivalent to the VCU118 eval board. There just isn't raw ic (single quantity) pricing available for a single Kepler GK110 but there is for the Virtex Ultrascale... – ks0ze Nov 09 '18 at 17:41
  • @ks0ze I agree. Tesla cards were not really widely deployed - they're a niche product with a very small market (compared to XBoxes and GTX gaming cards, for example). The point is that chips with a similar manufacturing process, die area, and transistor count are selling at very different prices depending on the total sales volume - products that sell larger volumes can accept lower margins (and, in fact, require them to stay competitive). This is not the case for niche products with few alternatives and not many buyers. – J... Nov 09 '18 at 17:47