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I followed the AMBA 3 APB specification to design my APB slave. Reading from slave requires several clock cycles to make the data ready for the bus, so I set my PREADY signal for one clock cycle when the data is valid (PREADY default is always low). However, the APB bus controller does not wait when PREADY goes HI. It keeps PENABLE for one clock cycle and terminates the transection. Any one has an idea what is wrong?

It is running on soft processor CortexM1 on Microsemi FPGA.

enter image description here

Nazar
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  • Indeed this is not according to the APB specs. It could be that this particular APB interface does not support pready. I have seen that in others. The reason is that halting a processor is expensive in logic and timing so sometimes it is not implemented to make things "easy" for the designer (pushing the burden on others). What does the documentation say? – Oldfart Nov 02 '18 at 14:05
  • @Oldfart Hm... Microsemi provided me with an [AN](https://www.microsemi.com/document-portal/doc_view/130033-ac335-building-an-apb3-core-for-smartfusion-csoc-fpgas-app-note) for implementing the APB3 on a SOC, which has a different processor. But again, the processor comes from ARM. I wonder if it is possible that the Microsemi coreAPB ignores that signal. – Nazar Nov 02 '18 at 14:11

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This is no a complete answer but too big for a comment:

I have designed countless AXI, AHB and APB modules. From what I can see the response to your RDY is wrong. The application note you mention clearly shows the support for wait cycles.

What I can think of is:

  1. The Cortex APB module is broken or does not support pready.
  2. The RDY you generate is not the one the core sees.
  3. The waveform does not correspond to what is really happening (which is more or less a variant on 2. above.)

My next step in debugging would be to try:

  • Remove the peripheral and tie pready low. Your processor should then 'hang' when accessing any APB address.

  • Make a APB peripheral which returns e.g. the address bits on reading and see if the read access for that works.

Oldfart
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  • Found similar [post](https://community.arm.com/tools/f/discussions/919/apb-confusion) – Nazar Nov 05 '18 at 21:50
  • So it looks you need to get info about the soft processor CortexM1 processor if it supports PREADY. – Oldfart Nov 05 '18 at 22:07