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Why is there no drive current available from the circuit below when R is connected to 0V?

Example from wikipedia

The last sentance in this extract from wikipedia states that

If R is connected to 0 volts it will have no drive current available to drive the next circuit; practical diodes need a bias current.

If diode A had +6V at the input, R was 1k and connected to ground; then A would be forward bias ("fully on" as +6v >> 0.7V required) leaving B and C in reverse bias. Providing the +6V rail was capable of supplying more than the (6mA) required for the resistor I would have thought that there would be current left over to drive the next circuit?

andowt
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1 Answers1

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It's not a problem with the OR gate itself. Think about what happens if the OR gate output is connected to a diode-based AND gate. What happens at the output of the AND gate?

andowt
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user201365
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  • Hi, thanks for the reply. I'm not entirely sure what you're getting at? Do you mean a configuration as follows: https://imgur.com/a/40iCUCY – andowt Oct 24 '18 at 14:38
  • https://electronics.stackexchange.com/questions/131860/diode-logic-gates – user201365 Oct 24 '18 at 14:55
  • That circuit shows the resistor from the OR gate being referenced to ground? – andowt Oct 24 '18 at 14:56
  • most practical logic devices are built out of cascading gates. The biggest problem is noise immunity, so you want as wide a hysteresis band as possible. setting those OR gate resistors to ground diminshes that value for succeeding gates, and since diode resistor logic is passive to begin with, you don't want to waste that margin. Look at a correct implementation of an AND gate and see how low the output can be driven if the previous stage can only pull down to 0V-recall your desired levels (at least in the above example are 0 and 6V, how will succeeding stages after the AND deal with it? – user201365 Oct 24 '18 at 15:03
  • So what you're saying is that the output of the AND gate can only pull down to 0.7V? I appreciate your comment from a practicality point of view but I still don't understand where the current availability comes into this? My confusion with the wikipedia entry is that instead of ground the pulldown at the output of the OR is connected to -6V – andowt Oct 24 '18 at 15:07
  • The problem is that you have a current limiting resistor that goes to that rail voltage. It forms a divider network with the pullup resistor on the AND gate, so the the output of the AND gate is the average of the two supply rails (if the resistors are equal). You don't get a nice ~0V output at the AND gate in that case. – user201365 Oct 24 '18 at 15:30
  • That makes sense, but the Wikipedia article implies that having a negative pull-down on the OR removes the current limitation. Given the wikipedia example with the OR pulled down to -6V and the AND pulled up to +12V if both resistors were equal you would still have the same problem? – andowt Oct 24 '18 at 15:35
  • That +12V could work it all depends on the pullup resistor value, but it is wikipedia, I get the feeling those diagrams were ripped out of some other source and who know what the context was, but since they don't define what the resistor values are, it would still be (potentially) functional. If you want to play around with it (and it quick, fun, and you learn new stuff) get LTspice from linear technology, it's free a nice somewhat nonstandard GUI, but it has a spice simulator which lets you check things out for yourself and also play those important what-if games with real-world models. – user201365 Oct 24 '18 at 15:41
  • Thanks for the recommendation, I've accepted as an answer – andowt Oct 26 '18 at 08:43