How is something level trigger vs edge triggered?

Question

I understand what they both are, but how exactly is something "made" to be edge triggered? I understand some computer architecture concepts, and while I understand individual components (gates/flip flops/etc...) I don't understand what makes something rising edge/falling edge triggered or level triggered for example?

Im more or less looking for a "Physical" reason that determines why one vs the other.

@Transistor I think OP wants the physical explanation of how the transistors inside a device act when they are edge vs level triggered? — a concerned citizen, Oct 22 '18 at 18:45
@aconcernedcitizen that is correct that is what I was looking for — msmith1114, Oct 24 '18 at 14:34

score 7 · Accepted Answer · answered Oct 24 '18 at 14:54

Consider this schematic:

schematic

^{simulate this circuit – Schematic created using CircuitLab}

The input of the AND gate is either L,H or H,L. Never L,L or H,H. So, the output is always L. Right?

WRONG!

Every gate has a propagation delay. A few nanoseconds.

What happens is the following.

Input is L. The AND sees H,L. The output is L.
Input has a L→H transition. The inverter has a delay. The AND sees H,H. The output is H.
The inverter finally propagated the H on its input. The AND sees L,H. The Output is L.
Input has a H→L transition. The inverter has a delay. The AND sees L,L. The output is L.
The inverter finally propagated the L on its input. The AND sees H,L. The Output is L.

So, this circuit is an edge-detector for the L→H transition. It creates a few nanosecond H pulse during that transition.

score 1 · Answer 2 · answered Oct 22 '18 at 18:43

In SOC systems which I have seen they work a bit different from what most people expect: They do NOT use the interrupt signal rising/falling edge immediately.

Completely a-synchronous interrupts first need to be synchronized. This is not needed with most internal generated interrupts as they are often generated by a circuit which is already running at the CPU clock.

Then the signal is delayed by one-clock cycle which give you the 'previous' state. Next a logic circuit checks if the current value differs from the previous one. If so you had an edge.

If the old state was low and the current state is high you have a rising edge.
If the old state was high and the current state is low you have a falling edge.

Here is some Verilog code:

module irq_edge (
   input  sys_clk,
   input  sys_reset_n,
   input  async_irqA,   // A-synchronous  interrupt
   input  sync_irqB,    // synchronous  interrupt

   // Outputs
   // Beware : high for only one clock cycle
   output rising_edge_A,
   output rising_edge_B,
   output falling_edge_A,
   output falling_edge_B
   );

reg meta_syncA,safe_syncA;

reg prev_irqA,prev_irqB;

   always @(posedge sys_clk or negedge sys_reset_n)
   begin
      if (!sys_reset_n)
      begin
         meta_syncA <= 1'b0;
         safe_syncA <= 1'b0;
         prev_irqA  <= 1'b0;
         prev_irqB  <= 1'b0;         
      end
      else
      begin
         // Sychronise async_irqA to system clock
         meta_syncA <= async_irqA;
         safe_syncA <= meta_syncA;

         // Delay for edge detection
         prev_irqA  <= safe_syncA;
         prev_irqB  <= sync_irqB;
      end
   end

   // Compare old and current value of signals
   assign rising_edge_A  = ~prev_irqA &  safe_syncA; // was low now high
   assign rising_edge_B  = ~prev_irqB &  sync_irqB;  // was low now 
   assign falling_edge_A =  prev_irqA & ~safe_syncA; // was high now low
   assign falling_edge_B =  prev_irqB & ~sync_irqB;  // was high now low

endmodule

And here is a waveform:

score 1 · Answer 3 · answered Oct 24 '18 at 15:10

The normal way to create an edge-sensitive flip flop is to combine two level-sensitive latches which are sensitive to opposite states of the clock.

To create a rising edge triggered flip flop, you would first have a latch which is transparent when the clock is low. The output of that latch would go to the input of a latch which is transparent when the clock is high.

How is something level trigger vs edge triggered?

3 Answers3