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When I read articles, FPGA comes with a specification-nm. For example, Xilinx 28nm Virtex 7 or 20nm UltraScale FPGAs. What does -nm means in FPGA?

JaeWon Kim
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    size of the transistor gate in nano-meters (one over a billion = 10E-9) – Alexander James Pane Oct 08 '18 at 07:51
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    This is by the way not FPGA specific but applies to all fabricated chips – po.pe Oct 08 '18 at 08:01
  • @Alexander Pane I know it is a one liner but this is a good answer to the question can I suggest you put it up as an answer so that the question gets flagged as answered. – RoyC Oct 08 '18 at 09:12
  • @AlexanderPane not really true for sub 28nm processes. Even for 7nm the gate ranged from 42 to 54nm depending on the fab. It lost most of its meaning since FinFET. Usually it's just calculated based on the size of the SRAM cell. – Dan M. Oct 08 '18 at 10:05

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It's the size of the gate of transistors inside the chip and so a name for the production process. Smaller gates mean more transistors inside a chip.

See here for more details:

what do the nm or µm for a process technology refer to e.g 22nm process technology for device fabrication

Alexander von Wernherr
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It means the structure width of the manufacturing process (I.e. the width of the transistor structures within the FPGA).

Adam Haun
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Stefan Wyss
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As pointed out by RoyC I'll expand the comment to a full answer, giving some more insights.

Any kind of semiconductor needs to pass through a production process. The process technology was historically associated to the length of the silicon channel between source and drain in field effect transistors. This has varied a lot in the last 5 decades, passing from a 10 µm in 1971 to the current 10 nm in 2017 and it is prospected to have a 5 nm technology by 2020.

Just to remind the length magnitudes:

  • 1 mm (milli-meter) = 10E-3 m
  • 1 µm (micro-meter) = 10E-6 m
  • 1 nm (nano-meter) = 10E-9 m
  • 1 pm (pico-meter) = 10E-12 m

Since technology has evolved in various aspects, also the transistors have. So how it is pointed out by Dan M, nowadays we continue with naming the process with a shrinking size, but this is not referred to the channel's length, but to the smallest element in the transistor or the size of the gate.

For more info you can check out these references:

Wikipedia general explanation on production process

Extra details on naming the process

I would also like to point out that the process doesn't continue linearly decreasing, since with smaller technologies more problems arise. There is a theoretical limit to this shrinking, since to create a transistor at least three elements (Source-Drain-Gate for FET transistors or Collector-Emitter-Base for BJT transistors).

I also report one interesting research on super small transistors:

In 2018, researchers at Karlsruhe Institute of Technology created a transistor with a working single atom gate

So actual research is already pretty close to physical limitations in transistors. If we need to push more, other technologies need to be discovered, making transistors obsolete.

You can find more research level technologies on this Wikipedia page.

Naturally this answer of process technology is not applied only to FPGA manufacturing, but to the whole integrated circuits manufacturing (FPGA, ASICS, CPU, GPU, etc.).

Alexander James Pane
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