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I have a design is that over-stressing (EOS) a PFET's (PMDT670UPE,115) rated Vgs by 50% (Vgs -12V, limit is -8V), I want to consider PWM'ing this part with 50% duty cycle in hopes of increasing the part lifetime!

We still would be saturating FET and providing EOS Vgs just trying to

  • reduce time spent at the EOS condition and
  • reduce temperature which (slightly) increases permittivity.

Can you conjecture if how PWM would impact the population of FETs operated at the unrated Vgs?

  1. Would it counter-intuitively reduce part lifetime (perhaps due to switching losses)
  2. might PWM'ing have a proportional extension of lifetime
  3. might PWM'ing have a significant / nonlinear extension on the PFET lifetime.
Andrew Sauter
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    Welcome to EE.SE. Since MOSFET's normally have a gate resistor, over voltage issues are handled by inserting a 12 volt zener diode from gate to source. –  Oct 02 '18 at 22:41
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    Other than insisting you add a zener to clamp the over voltage we have nothing pleasant to say. PWM will NOT increase the life of a MOSFET with a 50% Vgs overdrive. It only last because manufactures play it safe and add their own safety margin. You are putting your MOSFET in the danger zone. –  Oct 02 '18 at 22:45
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    Stay well within Vgs max and SOA during transitions and chose a lower RdsOn or better heatsink, – Tony Stewart EE75 Oct 02 '18 at 22:45
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    Please edit your question, and then update it to include the FET part number and explicitly state the voltage that you are applying from gate to source. I want to confirm that you really are driving it over its rated voltage by 50%. There are multiple voltages listed, and perhaps you are getting confused (no offense meant). – user57037 Oct 03 '18 at 02:36
  • What precisely do you mean by "saturating FET"? – Andy aka Oct 03 '18 at 07:01
  • I see now that is a P-channel MOSFET with logic gate drive, so use a 5 volt zener instead of a 12 volt to protect your device. -12V is 50% greater than the -8V max limit for the device. PWM or not, it will not live long. –  Oct 03 '18 at 20:38
  • Thanks for updating the question. Now that it is confirmed that you are indeed going over the absolute maximum gate source voltage, the answer is very straightforward: don't do that. I do not think it matters much whether you PWM or not. What matters is minute details in the gate region that vary from device to device. Maybe some MOSFET's can stand it. But most likely 12V will blow-up quite a few of them. If you are having success with the design the way it is, well, I guess you are lucky. If you have not yet launched this, I urge you to modify it prior to launch. – user57037 Oct 04 '18 at 03:13

1 Answers1

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TI's AHC/AHCT Designer's Guide cursorily describes what happens when you overstress a MOSFET's gate (in this case, the input transistor of a logic device):

Input voltages greater than 7 V must be avoided to preclude damage to the gate oxide of the input stage. This damage is not necessarily permanent, but will adversely affect the expected lifetime of the circuit. The gate oxide of AHC devices is only 200 Å thick. An input voltage of 7 V corresponds to a field strength over the gate oxide of 350 kV/cm. Although breakdown of the oxide is expected only at input voltages above 10 V, electrons tunnel increasingly into the gate oxide at field strengths greater than 350 kV/cm, influencing characteristics of the transistors and causing failure.

So as long as you do not reach the breakdown voltage, the primary failure mechanism is electromigration, and using PWM will delay (but not prevent) failures.

But if you reach the breakdown voltage, time does not matter. And the datasheet will not tell you where the actual breakdown voltage is, or the statistical distribution of this value. (In the example above, the breakdown voltage might be 43 % above the rated voltage.)

CL.
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