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In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized before (using the main clock):

always @(posedge clk_100Mhz_i)
begin
    // Synchronizer chain... hopefully    
    clk4_del0 <= clk4_77_i; // SysClk from ext pin
    clk4_del1 <= clk4_del0;
    clk4_del2 <= clk4_del1;
end

// Used to clock internal regs
assign clock_4_77Mhz = clk4_del2;

// Sample
always @(posedge clock_4_77Mhz)
begin
    timerIdx <= timerIdx +1;
end

Unfortunately I get the following warning:

Warning (332060): Node: X8255_top:x8255|clk4_del2 was determined to be a clock but was found without an associated clock assignment....

I also get a warning about an unconstrained clock. I tried to use what the Timing Analyzer suggested and added the fourth line to my .SDC:

# Constrain clock port clk_25MHz_i
create_clock -period "25.0 MHz" -name clk_25MHz [get_ports clk_25MHz_i]
create_clock -period "4.77 MHz" -name clk_4_77MHz [get_ports clk_4_77_i]
create_clock -name {X8255_top:x8255|clk4_del2} -period 210

without success.

What am I doing wrong?

fhw72
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  • What do you know and need to learn? https://www.eevblog.com/forum/microcontrollers/quartus-ii-clocks/ – Tony Stewart EE75 Oct 01 '18 at 15:42
  • You should define the `clock_4_77Mhz` signal as clock, not the incoming `clk_4_77_i`. I am not familiar with Altera Quartus what the exact syntax is to define an internal signal as clock. Beware that due to the synchronization your mark-space ratio will be affected and thus can be shorter then 209ns. – Oldfart Oct 01 '18 at 15:43
  • Try posting FPGA QUESTION [HERE](https://area51.stackexchange.com/proposals/125912/fpga?referrer=M2EwM2FlOWQwMWY3MmExMzFhMGYzYjdhMmZjNWIzYzI2ZTZiZjhmNGU4Y2M4M2JjNDgxZjQyYTIyMzA2MWUwNzX3hnbYNR7EdlfF6m4rBq-JYXjqFwvBDZB5QkiDqKuf0) – Bill Moore Jul 12 '21 at 14:00

1 Answers1

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Likely, it is because clk4_del2 is not used as a clock (e.g. connected to a clock input of a DFF), but as an intermediate signal... you may even find it gets optimized-out (in your reports?) as it is a continuous assignment. Unless you use a primitive (clock buffer maybe) and tell the tool not to remove the buffer, and thus the buffer contributes to path delay (and it forces a "name change"), I don't think it will resolve as you intend.

Alternatives, you probably realize already and are only asking because want to keep the RTL as-is, but jic:

If you were to replace your clk_4_77MHz clocked process with clk4_del2 you should find that the constraint resolves properly.... but, then you have the dangling net of clk_4_77_MHz (assuming it isn't used anywhere else) and that is kind of ugly.

If you like your clk_4_77MHz (i.e. it is more descriptive), eliminate the clk4_del2 and replace the assignment: clk4_del2 <= clk4_del1 with clk_4_77MHz <= clk4_del1.

Either that, or just leave everything the way it is and remove the constraint for clk4_del2, and your intent, and the tool's interpretation of your intent, should remain the same.

CapnJJ
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