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Many sources claim that when the base-emitter voltage becomes smaller than approximately 0.6V-0.7V, the bipolar junction transistor goes in the cutoff region and there is zero base and collector current.

Of course this is not completely true, since there will be some (exponentially decreasing) current for lower values of Vbe, and this exhibits the characteristics of diodes operated at low voltage (with an exponential I-V characteristic).

Does the Ebers-Moll model accurately predict the behavior of the BJT in cases where Vbe is so small that the base current becomes on the order of pA (10e-12 A)? In general there is a current gain parameter called beta ~ 5 - 100 which relates the collector current to the base current, but does this beta decrease if the base current becomes extremely small?

I am asking this because I have a particular application where I need extremely low currents, and I am not sure if the simulator (Cadence Spectre with foundry-provided npn models) is reliable in this unusual region of operation. I know that it uses the Gummel-Poon integral charge model, but this should be close to the Ebers-Moll model at low currents, I expect.

Tob Ernack
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  • Tob, are you working with a foundry? Because they don't usually give out their models easily, unless you are working with them. If so, their models tend to work well even on the low currents you mention. But ask, of course. (Likely VBIC or Philips MEXTRAM models. Or, in some specialized cases, HICUM.) Also, regarding Ebers-Moll, you could look over what I [wrote here](https://electronics.stackexchange.com/questions/305693/dependence-of-transistor-current-gain-on-operating-conditions/305720#305720) about low currents and the problems modeling them. – jonk Sep 17 '18 at 23:00
  • Finally, be aware of shot noise issues. Anytime a current crosses a PN junction, it's "randomized" (poisson) and leads to noise. For example, suppose you have a base current of \$10\:\text{pA}\$. Then you can expect \$2\:\frac{\text{fA}}{\sqrt{\text{Hz}}}\$ on that score alone. At a bandwidth of, say, \$1\:\text{kHz}\$ this would imply getting very near 1% of your base current as noise due only to this effect. If these low currents result from a diode detector, you can also expect another quantum effect from the light itself: a kind of "flocking," since bosons can be in the same quantum state. – jonk Sep 17 '18 at 23:09
  • I work (indirectly, through the university) with a foundry (signed an NDA), and I am using the models provided with the design kit from the foundry, but I believe from reading the Spectre simulator documentation that the bjt model used is "integral charge Gummel-Poon model". The foundry just provides specific parameters to a bjt instance in their custom .scs model file. – Tob Ernack Sep 19 '18 at 13:41
  • You should probably ask your foundry, then. They know what they gave you. Gummel & Poon's seminal 1970 paper is titled, "An integral charge control model of bipolar transistors." Spice uses an improved GP model, so I'm not even sure if your simulator is up to date in that respect, from what you write. Note also that, for example, LTSpice includes a VBIC and MEXTRAM models, as well. I know that the Spice GP model includes low current effects. I just don't know how good those models are, since I've not attempted validating modeled collector currents under a nanoamp in a practical circuit. – jonk Sep 19 '18 at 16:46

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I understand your issue. Personally I would not expect either model (Ebers-Moll nor Gummel-Poon) to produce accurate results with such low currents. The models are neither designed nor verified for that region of operation.

Also I think that leakage and temperature related issues (and we all know that leakage and temperature have strong relations) will influence the currents dramatically. Often these effects are poorly modeled.

And even if the models could support accurate modeling at such low currents then the question remains if the model parameters are in any way reliable. If the transistor's manufacturer (foundry) did not measure and extract those parameters at such low currents then no one can say anything about reliability of the models.

Bimpelrekkie
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  • I see, in that case the only way I will know for sure is if I implement the circuit and experimentally verify it. Though I'd prefer not having to do that if it can be avoided. In my application, I don't really need to have precise values for the current and for beta, but I do need to be sure that the base current does not go above a few pA, and that the collector current will still have some proportionality to this base current. – Tob Ernack Sep 12 '18 at 14:27
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    Since you're doing things in the pico-ampere range, leakage currents matter and those currents can find their way through even some dirt on your PCB. You may find this EEVBlog video interesting: https://www.youtube.com/watch?v=QFOH8n43kY4&t= as it shows what a design needs to operate properly with very high resistance values and extremely small currents. – Bimpelrekkie Sep 12 '18 at 16:07
  • Do these leakage currents also arise in integrated circuits instead of PCBs? I guess you have a point, that if there is another leakage path, such as small conductance across the inter-metal insulation layers then I would need to worry about this as well... – Tob Ernack Sep 12 '18 at 16:17
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    *Do these leakage currents also...* I would turn it around and say: you're lucky if they're **not** there. You might know that common resistors you can buy go up to 22 Mohm (that's the highest I have here), special ones might go up to 100 Mohm (just my guess). Let's say I have 1 Volt and 100 Giga ohm (1000x more than 100 Mohm) that 1 V across it already results in 10 pA. So the trick is to stay above 100 Gohm, that's a challenge! – Bimpelrekkie Sep 12 '18 at 16:33
  • Indeed you would need very large resistances for that. So I suppose you're suggesting that typical insulators used between metal layers won't be good enough to avoid these sorts of leakages? – Tob Ernack Sep 12 '18 at 20:24
  • I should perhaps mention that my application is related to charge storage in floating gate devices (so it's a kind of memory device, and I need retention times of a few hours). This is why I need to leak as least charge as possible, while being able to measure it. In principle you could implement some kind of refresh operation to set back the charge to a fixed value, but I have constraints on how frequent this refresh rate should be, hence I am looking for ways to minimize the leakage current as much as possible. – Tob Ernack Sep 12 '18 at 20:26
  • Come to think of it, maybe I should ask a separate question for that as well, perhaps there are better approaches than what I've been trying so far. The obvious approach was using MOSFET instead of BJT, but due to the very small gate thickness that comes with the process, the gate leakage current is too large. – Tob Ernack Sep 12 '18 at 20:29
  • If you're going to use off-the-shelf components for this experiment then you can forget about it. **ALL** MOSFET based devices need and therefore have ESD protection diodes. These diodes **leak** so your gate charge **will** leak away or more charge will leak onto the gate. The only way to store a charge on a (real floating) gate is how flash memory does it. It uses a secondary fully isolated gate (no connection to anything) and these a high voltage causing break through of the SiO2 to get a charge on that secondary gate. – Bimpelrekkie Sep 12 '18 at 20:48
  • Fortunately I am not constrained with off-the-shelf components. I am implementing this as part of a custom integrated circuit so I have control over stuff like the geometry of the MOSFET itself, and I can choose where or where not to put ESD components. – Tob Ernack Sep 12 '18 at 20:51
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    *So I suppose you're suggesting that typical insulators used between metal layers won't be good enough to avoid these sorts of leakages?* On-chip metal layers are separated by SiO2, I think that would provide enough isolation. The problem is the devices in the silicon, diodes and MOSFETs all have **leakage currents** and though small, they will be much larger than the currents you're interested in. – Bimpelrekkie Sep 12 '18 at 20:52
  • Ah yes! I am indeed particularly worried about the leakage currents coming from MOSFET and diodes. By the way I asked a separate question more specific to what I really need, if you're interested. – Tob Ernack Sep 12 '18 at 20:54
  • OK, do note that **not** using ESD protection on gates can be done but is bound to give issues. The foundry might simply not allow it. Also during IC manufacturing charges can build up (plasma etching) on connections like when etching vias. So sure, you can design what you want but in my opinion you will have issues. Only if you would be using a **very** old process with very thick gate oxide you might get away with it. – Bimpelrekkie Sep 12 '18 at 20:56
  • I see. So my best bet is really to just find an older process that uses thicker dielectrics? Currently I am kind of stuck with the process I have, but it might be possible for me to switch to another one if I am sure that doing this on the current process is truly infeasible. – Tob Ernack Sep 12 '18 at 20:58
  • National Semiconductor's Bob Pease happily wrote of National's opamps with 10^-16 amps input leakage. Check on that. This was about 30 years ago, thus large geometry process. – analogsystemsrf Sep 13 '18 at 05:15