This is building on the other answers so far, but just my thoughts.
Given your budget, and the desire to compete with an entity who's budget is nearly 40X your own, you should not try to use exotics for your application. The major costs in designing this ASIC are going to be:
People. I assume you will be paying people to work on this full time as this is not a project that can feasibly be undertaken as an evening project (not withstanding point 2 below). You will need HDL developers, verification engineers, and implementation engineers. All of these are specialised skills with corresponding price tags. In particular, implementation engineers for exotics are (very) low in quantity and high in demand (especially if they're good). Don't expect much change from $1-5M (depending on location) per year.
EDA tools. These are expensive, just to license. You also need a lot of them, and multiple seat licenses. HDL compilers, RTL synthesis tools, simulators, layout tools etc. Each license is likely to be on the order of $100K per seat. Don't forget you also need the computing power and infrastructure to run them as well; you will need a pretty powerful cluster.
Design. Most tools and process design kits are mature for Si given the volume and revenue for this market. For your exotic, expect less-than-ideal models, especially for cutting edge process nodes. You will need to develop or buy standard cells for your exotic substrate. There will be many fewer than for Si.
Manufacture. There are speciality exotic fabs, but they are just that: special. The volumes are low, the wafers are (much) smaller, and costs are much higher (a rough estimate is 100-1000X per mm\$^2\$ compared to Si).
Even after this, there's little guarantee that you'll get the improvement you think you'll get just by running faster. A lot of very clever people have invested a huge amount of time and money in Si, and you'll be re-inventing the wheel for a lot of things (e.g. standard cells, power control etc) and probably be doing it worse. Fabs will often provide standard cells optimised for their process; it would be foolish not to use this. This will erode the advantage of using the exotic in the first place.
Unfortunately, open sourcing the design code doesn't allow you to manufacture the ASIC without a lot of other investment. Now, your $1B competitor can eat a lot of these costs and even if you open source the RTL, they can do the rest of the things which you simply can't open source. For example, semiconductor fabs are very cagey about releasing their in-house process models. You should do a very thorough audit as to the advantage of open sourcing in this case; manufacture simply doesn't scale in the same way software distribution does so the pros and cons are very different.
To answer your questions:
Budget limits everything (of course). Given the disparity to your hypothetical competitor, $30M would be much better spent on high quality people to develop a good architecture rather than trying to get "free" performance from the materials and process used. As my comments above hopefully illustrate, this "free" performance will be anything but free!
Good architecture will mitigate a lot of the advantage of going to an in-house exotics design. There is still potential for scaling in GaAs and other exotics. This may become relevant in the (near?) future - keep your powder dry to take advantage of that.
SiGe is closer to Si, so you may be able to use this more freely, although it will still be more expensive than Si. GaAs is more specialised, and is usually used for its high ft in RF designs where area cost is less of a concern. Going from 100 nm to 10 nm gives you (to a first order) you 100X more transistors to implement your excellent architecture. Of course, architectural improvement usually scales as \$\sqrt{N_\mathrm{transistors}}\$, so probably around 10X performance gain overall. Bear in mind though, that even $1B is nowhere near enough to push a fully new process through, so the chances are your competitor will still be using Si.
SERDES for 4096 bits is a lot of registers - this is going to cost a lot of power and area for no performance benefit on your exotic wafer. Given you can fit whole processors in fewer than 4096 registers (let alone 8192), this illustrates the issue there. Area is much cheaper on Si.
Going to smaller transistors means higher power density, hence more need for power control, i.e. bits that are turned off (dark silicon). A lot of work has gone into analysing and reducing power consumption while maintaining acceptable performance. A critical factor is your expected activity. Will it be working full throttle 24/7, or will it be periodic? This will make a big difference to your design.
A $1B competitor has no care about obfuscation if the reward is high enough. Don't be hubristic in thinking your design is the perfect implementation.
To summarise, you should spend your money on the people and tools that develop your architecture and algorithm (don't forget that!). This is likely to provide the best return for your relatively constrained budget by leveraging the massive investment in both tools and process for Si. Simply using a faster material is highly unlikely to give you the improvement it seems on paper by raising the clock rate, given all the other steps in designing and making an ASIC.
Personally, I would target a "cheap" Si node (probably something like 22 or 28 nm) to get your design up and running. If it's successful, you can use the scaling benefits to go to smaller (and more expensive) nodes, leveraging the work you've done already and the work done by the fabs. In the interim, as you are developing an ASIC, you can push the operating conditions wider as well, as compared to a CPU/GPU which has to work across a huge and unknown range of conditions. For example, you can specify the cooling equipment that should be used. This will further erode any advantage by going to higher performance materials.
