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When powering down a board, for ICs that have multiple supply voltage rails, why do they need a specific power down sequence?

Typically in complex motherboards, there is a CPLD doing the job of this power down sequencing.

Why don't we just pull power off everything at once?

JRE
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Neil Dey
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  • It depends on bulk storage energy and possibility for overvoltage on lower voltage interfaces that drain faster. A DC ok circuit can put the interfaces as inputs when false or some safe mode or as suggested by chip Mfg for power sequence if applicable. – Tony Stewart EE75 Aug 14 '18 at 21:52
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    It's like when you try to kill a living creature, they panic, struggle and cause damage. The time between you pull the power and everything is silent is quite significant on the scale of CPU cycles. A rogue system can cause some serious to the data or equipment it manages so better notify and prepare them for power loss in a well defined way. – user3528438 Mar 31 '19 at 18:29

2 Answers2

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Because you could have a higher power rail bleeding out into a space that is only designed for lower voltages and burn out transistors. It's also good to avoid short term overcurrent on power down.

Power supply sequencing can prevent damage and extend the life of your power supply and any sensitive DSPs and FPGAs in your design. In addition to controlling the startup timing to control current draw, the power supply rails need to stay within the voltage tolerance requirements of FPGAs. These tolerances have become tighter with new process technologies, to the point where 3% total core voltage tolerance may be necessary. Sequencing the power supplies in a system can be accomplished in several ways Source: https://www.powerelectronicsnews.com/technology/power-supply-sequencing-for-fpgas

Voltage Spike
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There are often devices connected between different rails that have unwanted current paths that can be energized if the rails are not powered up and down in the proper sequence.

Think of an CMOS logic pin that can cause destructive latchup if an input is applied and then power is applied to the chip.

It can often be avoided by careful design and somewhat of an increase in complexity (perhaps at a slight cost in performance), but that is not always done.

One particular tactical grade military device I've worked with requires significant energy storage to maintain the proper sequence, so we had to add a lot of reservoir capacitance to meet the specifications under all possible conditions (mistakes can be very expensive).

Spehro Pefhany
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