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I have a question regarding timing analysis for DDR3 and DDR4 signals. How do we do timing analysis to see if all setup and hold requirements are fulfilled correctly, considering they have write levelling algorithms to take care as well. Suggeat some method and tools than can assist an engineer to analyse for the timing of the DDR3 and DDR4, specifically where memory device and controller are on two different PCB connected with board to board connectors and not through conventional DIMM or SODIMM

P. Shubham
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    Often the processor has a calibration routine you can run through. I worked on a design with a TI Sitara MPU and DDR3, and TI provided software to do the tuning. You run it through, and it finds ideal values. This typically requires some special functionality in the DDR macro on the MPU so should be documented in the datasheet/manual somewhere. If its a mainstream processor though, they probably have code you can use already. If calibration passes, and an extensive memory test (walking ones, walking zeros, address as data etc) passes, you can usually consider your design qualified. – Oliver Aug 09 '18 at 07:13

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The manufacturer of the DDRx controller should provide design constraints for PCB layout, covering the clocks, address, control, data and DQM signals. If not, you may be able to infer them by putting together the DDR controller's DIMM routing guidelines with the appropriate JEDEC DIMM spec. Follow these guidelines to achieve the required impedances, path lengths and spacings in your routing between the controller, the board-to-board connector, and the memory devices.

Verify your design by performing IBIS modelling of the whole interconnect (this will require signal integrity expertise) and comparing results with your design constraints, and with known good layouts (usually based on standard DIMMs).

The controller's calibration/levelling is built on an assumption that PCB layout constraints have been followed exactly. It may provide diagnostic registers to allow you to verify the levelling outcome at runtime. I have found ECC to be very useful for design proving.

A good PCB layout tool will enforce constraints as you go and will simplify the serpentine routing that is usually necessary to meet path length constraints. I have seen many right-first-time DDRx layouts done quite quickly with Cadence tools.

amb
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