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As far as I know there are two major buses - AMBA/AXI and Wishbone. While AMBA/AXI has proven itself in almost every ARM chip, I didn't find some numbers for Wishbone. Are there any benchmarks or real (ASIC) implementations of Wishbone?

Bus requirements: - patent/license free; - can connect endpoints with arbitrary bit sizes (e.g. 64 bit to 32 bit); - fast (can be used to interface ddr3 controller)

user37741
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  • Welcome to EE.SE! Keep in mind that questions about optimization (i.e,. *"What is the best ...?"*) require a definition about what problem dimensions are to be optimized for your application, such as size, speed, energy consumpation, user experience, etc. Since these can't be optimized all at once, you need to have a good idea of which ones are most important to you, and be able to articulate that clearly to us. – Dave Tweed Jul 22 '18 at 21:10
  • @DaveTweed just edited – user37741 Jul 22 '18 at 21:14
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    See also: [CoreConnect](https://en.wikipedia.org/wiki/CoreConnect) (by IBM) e.g. Processor Local Bus (PLB) or [Avalon](https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/mnl_avalon_spec.pdf) (by Altera/ now Intel). – Paebbels Jul 22 '18 at 21:35

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Definitely AMBA.

Wishbone has synchronous writes and a-synchronous reads whilst AMBA has both synchronous. In an SOC design you want everything to be synchronous.

On Wishbone you continuously have to add in a wait cycle for the data to come back from a register or from memory*, whilst in AMBA the data flows without waiting.

The write cycle in AMBA is less adapted but:

1/ You read a lot more then you write in SOCs

2/ You can delay/store a write address, but you can't predict read data.

Between AXI/AMBA, AMBA the simplest to implement. AXI is nasty as it looks so simple but is difficult to get right.

*All on-chip and on FPGA memories are synchronous these days.

Oldfart
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  • You mention that Wishbone needs a wait cycle for data to come back because of the slave's synchronous nature, but AMBA has exactly the same requirement (data flows without waiting is just plain wrong and seems to be a deliberate smear against Wishbone). If your memory and interconnect is fast enough, Wishbone B3, B4 non-piped, and B4 pipelined *all* support single-cycle access times. Were this not the case, my Kestrel-2 and Kestrel-2DX projects would not function at all; they are existence proofs that Wishbone B3 supports single-cycle read and write accesses. – Samuel A. Falvo II May 15 '19 at 03:29