Data during AHB Busy state

Question

I have a question regarding the data during the BUSY state in a AHB bus. Consider the following example of an AHB master writing data onto an AHB slave:

TIME:        T1        T2        T3        T4
HTRANS:     NSEQ      BUSY      SEQ       IDLE
HADDR:      0x01      0x02      0x03      OxO4
HWDATA:     dataA     dataB     dataC     dataD
HREADY:       1         1         1         1
HBURST:     INCR      INCR      INCR      INCR

In the above case will the data written be as follows:

ADDR        DATA
----        ----
0x01        dataB
0x02        XXXX
0x03        dataD
0x04        XXXX
0x05        XXXX

Or will the data written be as follows:

ADDR        DATA
----        ----
0x01        dataC
0x02        XXXX
0x03        dataD
0x04        XXXX
0x05        XXXX

Or is it in some other way the data is written.

Thanks in advance.

score 1 · Accepted Answer · answered Jun 07 '18 at 13:34

The busy signal is part of the address bus and therefore relevant during the address phase, not of the data phase.

Thus it is your first case where no data is written to address 0x02 which happens. There is an example in the AMBA specification (I have rev 2.0 on page 3-10):

The busy cycle in T2 is ignored. Consequently the data in T3 is drawn as blank.

Data during AHB Busy state

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