4

I'm working on a simple neuron implementation on a Xilinx Spartan-3E starter kit and getting the warning in the topic. Can anyone explain me why I am getting this error?

My code:

module NeuronMdl #(parameter NUMBER_OF_INPUTS= 2) (
input wire[NUMBER_OF_INPUTS:1] x,   // Number of input bits.
output reg y    // Output.
);

reg signed[7:0] w[NUMBER_OF_INPUTS:0];  // Weights array, w[0] is bias so there's no input as x[0].
reg signed[7:0] yTemp;


initial begin   // Initial values for an OR Gate.
    w[0]= 8'h00;
    w[1]= 8'h01;
    w[2]= 8'h01;
end // initial

always @(x) begin   // Everytime there's a change in the input.
    yTemp= w[0]+ w[1]* x[1]+ w[2]* x[2];    // Need to find a way to generate this for varying input bits.
    y<= (yTemp> 0)? 1: 0;   // Output only 1 or 0.
end // always
endmodule

UCF file:

# slide switches
NET "x<1>" LOC="L13" | PULLUP;
NET "x<2>" LOC="L14" | PULLUP;

# leds
NET "y" LOC="F12";          # led 0

And the warnings I'm getting:

WARNING:PhysDesignRules:367 - The signal <x<1>_IBUF> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <x<2>_IBUF> is incomplete. The signal does not drive any load pins in the design.
WARNING:Par:288 - The signal x<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal x<2>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
W5VO
  • 18,303
  • 7
  • 63
  • 94
  • 1
    Some things to check: Check for warnings earlier in the process. Use Planahead to look at your logic and see if it's wired up as you expect – Martin Thompson Aug 13 '12 at 12:48

1 Answers1

2

The "initial" block is possibly being ignored in synthesis, so the weights "w" are really being initialized as zero, so the inputs "x" are being synthesized away, since their value don't affect anything (and "y" is always zero).

To fix it, declare the weights as constants until you are ready to put some logic that drives them.

This is one of those cases where simulation is different than synthesis, courtesy of the "initial" statement, which should only be used in testbenches.

apalopohapa
  • 8,419
  • 2
  • 29
  • 39
  • 1
    Xilinx XST can handle initial blocks for synthesis - see page 228 and 229 of [this document](http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/xst.pdf) – Oli Glaser Aug 14 '12 at 22:06
  • It may not be inferring a flip flop though (even if declared as reg). I don't have ISE installed to check. – apalopohapa Aug 15 '12 at 01:30