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I would like to know more about the resistors again in parallel with the MOSFETs in the picture. The Si2365EDS is a P-channel transistor and the 2N7002 is a N-channel transistor. How does one calculate the resistor in parallel with them? How does one know when the value of the tension of VGS is definied and the tension in which the state of the MOSFET will act as a closed circuit(when used as a switch)?

jellybean
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    There aren't any resistors in parallel with the FETs, or at least not in parallel with the DS path. Are you talking about R1, R2 and R3? What, exactly, is the circuit supposed to do, and how do you think it works? – WhatRoughBeast Mar 09 '18 at 23:05
  • This is an on and off switch and yes i am talking about R1, R2 and R3. – jellybean Mar 09 '18 at 23:15
  • If i understand correctly, if the tension of R1 is negative for any valeur between 0 to -8V, Q1 will be a closed circuit and it will be the same for Q2 and Q3 if the tension of the resistors in parallel to them is positive – jellybean Mar 09 '18 at 23:18
  • somewhat related: [How do I calculate the required value for a pull-up resistor?](https://electronics.stackexchange.com/questions/23645/how-do-i-calculate-the-required-value-for-a-pull-up-resistor) In general, look up these terms: *pull-up resistor* and *pull-down resistor*. – Nick Alexeev Mar 09 '18 at 23:19

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The values of gate-source resistors are generally not precisely calculated. Their function is simply to ensure that, with no external voltage applied (and note that "no voltage" does not mean "zero voltage") the leakage current from the gate will produce a voltage sufficiently low (less than 0.1 volt, let's say) that the FET will not turn on.

In the case of the p-type, the datasheet gives a gate current at 4.5 volts of 1 uA. So a 100k dropping 1 uA will only have about 0.1 volts, and the FET will remain off. But, you say, the gate is then not at 4.5 volts, so how does this count? Note that, with 8 volts on the gate the leakage current is 10 uA, so it's reasonable that, for a lower voltage than 4.5, the current will be even less. Like I say, these aren't precision calculations.

100k is a nice convenient value, and you can get them in surface-mount packages (not always available for much larger values), so the designer went with it.

A smaller value could easily be used, such as 10k or even 1k. However, you don't specify what is driving PB0, so depending on source you might want to avoid low values. And if the voltage source is actually a battery (as your symbol indicates), R3 should generally be larger rather than smaller to minimize battery drain. In this case, using 100k will work for all 3 FETs, so there was no need to provide tailored values to each.

The exact value used might well depend on the rest of the circuit. For instance, if whatever provide PB0 uses 10k resistors and no 100ks, you might well use 10ks just to minimize the number of different parts you have to order.

So, like I say, these values aren't something to spend a lot of time on. Almost anything below about 1M will work just fine. I suspect the designer uses 100k reflexively for GS resistors, and assigned the value almost without thinking.

WhatRoughBeast
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