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I wanted to automatically Identify some structures in HDL code (Verilog/VHDL), let say an adder. I need to automatically detect how many adders in the design. I am not sure from where to start, should I like convert my code into AST (abstract syntax tree) look for pattern and then convert it back to Verilog/HDL ? can anyone mention an example or a small tutorial on how to do such tasks ? Thanks

Hachani Ahmed
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  • GHDL offers [something](http://ghdl.readthedocs.io/en/latest/using/Simulation.html#cmdoption-ghdl-disp-tree) that might be useful to you. I can't say anything about how useful it is, I only used it once. – koalag Mar 02 '18 at 02:55
  • You can compile and check the rtl schematic of ur code. It will give you the digital blocks being implemented if that's what you meant by "structure" – Sourabh Tapas Mar 03 '18 at 01:20
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    Identifying adders is more complicated then just creating an AST or similar structure. You need to synthesize the HDL description. This means translate HDL into a schematic. Then you can identify structures in the schematic like adders. Can't you parse synthesis log files? These contain messages like signal xyz was translated to an adder. – Paebbels Mar 03 '18 at 14:49

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