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Correct me if I am wrong but so far, I've learnt that some ICs can source current while some can only sink (open-collector) while others can do both. And it is decided by looking at the datasheet, Ioh and Iol readings, which should be in mA values to glow an LED. But I sense I'm wrong since an LED should not be the only factor to decide sink/source concept. To add, Ioh and Iol can be of different values (like one in uA while other in mA), so it is not related to heat generated in the IC since heat generated is directly related to current in the IC. So my question is, what actually decides whether an IC will be able to sink or source while Voltage outputs for low and high states are similar for all of them! So what exactly decides whether the current will be uA even when output is high or in mA even when output is low?

[edit]We say that the IC is an open-collector, so even when the output is HIGH voltage output, it wont be able to source since Ioh will be in uA (like in case of 7489 RAM). So, what exactly decided this uA current while current should be related to external load resistance attached to output which is in our control. What exactly limits this current to uA? It should not be heat since in case of LOW state, current is in mA, which should actually burn the IC if we go by logic of heat for uA current in high state.

Peace
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    If the digital output has only a switch to ground that can be open or closed, then it can only sink current. If it only has such a switch to the plus supply, then it can only source current. If it has two switches to both rails, then it can sink and source current. – jonk Feb 17 '18 at 10:55
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    The IC designer decides. If he thinks it only needs to sink current, he'll save money (and power) by leaving out the pullup transistor. –  Feb 17 '18 at 14:17
  • Often the marketing or applications people report on customers' evolving needs, to allow a heads-up and get ahead of the competition. Thus the IC designer may have little choice about the IC behavior. – analogsystemsrf Feb 18 '18 at 02:39

3 Answers3

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It is the circuit on the IC / chip.

This is a simplified example of what a typical output circuit of any CMOS IC looks like:

enter image description here

A is some logic signal coming from the internals of the IC.

Q is connected to the output pin of the IC.

This is an inverter and it consists of a PMOS (top transistor with the small circle) and an NMOS transistor.

When designing this circuit I can choose the geometry (size, W/L) of both transistors and this geometry dictates how much "resistance" the transistor will have when it is switched on.

Suppose I make the NMOS (bottom) very large and strong but the PMOS very small.

Then the NMOS can draw a lot of current meaning Iol will be large

Then the PMOS cannot supply much current meaning Ioh will be small.

For an "open drain" output, I can simply leave the PMOS out (or the NMOS but that is quite unusual).

Bimpelrekkie
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    So it means that the concept of source current aka Ioh and sink current aka Iol comes from the transistors inside the ICs? I also want to know that since we have a non-zero values for each Ioh and Iol in the datasheets, is it right to say that all such ICs can do both sinking and sourcing of current, but we call it open-collector since source current (Ioh) is very small for practical use? – Peace Feb 17 '18 at 11:03
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    *is it right to say that all such ICs can do both sinking and sourcing of current* No, the design of the circuit dictates the large value currents. The small Ioh on an open collector NPN or open drain NMOS is the result of **leakage currents**. Devices are never "completely off" there's always some small current leaking through. That small Ioh is due to this leakage, in a datasheet you might find the **maximum** value of this current, like a few uA. In practice the current is usually much smaller. Leakage currents are unpredictable so the datasheet number is the worst case value. – Bimpelrekkie Feb 17 '18 at 12:57
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I thought I'd start out with an adaptation of the four-quadrant chart often seen for other reasons in electronics. In the following chart, the \$x\$-axis is for current (into or out of the pin) and the \$y\$-axis is for voltage at the pin (relative to the voltage at the other end of the load that's attached to it.)

enter image description here

There are four possible quadrants. Keep in mind here that I'm discussing digital systems with \$V_\text{CC}\$ (highest possible voltage) and ground (lowest possible voltage.)

  1. In quadrant 1, the pin voltage is being driven above the voltage at the other end of the load and it is sourcing current into the load.
  2. Quadrant 2 is never a good thing for an output pin (and isn't used.)
  3. In quadrant 3, the pin voltage is being driven below the voltage at the other end of the load and it is sinking current from the load.
  4. Quadrant 4 is never a good thing for an output pin (and isn't used.)

Some outputs are only capable of actively operating in quadrant 1 (rarely found, but certainly possible.) Some outputs are only capable of actively operating in quadrant 3 (frequently found and often called "open-drain" or "open-collector" outputs.) Some outputs are capable of actively operating in both quadrants 1 and 3 (quite common.)

For outputs that are capable of actively operating in both quadrants 1 and 3, it's sometimes possible to configure them so they actively operate in only one quadrant, or the other.

I've used the term "actively" to mean that they use an active transistor circuit of some kind. There is another term, "passively," that can be used for simple parts such as a resistor. So, for example, you can take an output that is open-drain (quadrant 3 operation only) and add a sourcing resistor to that pin, tying the other end of the resistor to \$V_\text{CC}\$, in order to provide an "active-LO" and "passive-HI" output. Now, it can both sink and source current! But it cannot source current nearly as well as an output pin that operates actively in both quadrants 1 and 3, because a sourcing resistor is not as good as a sourcing transistor circuit when sourcing current.

So as you can see there are a variety of mechanisms for an output pin. And you can modify output pins that are limited to one quadrant or another, adding a resistor (between the output pin and ground or \$V_\text{CC}\$) to provide a small measure of added behavior in the opposing power sourcing quadrant.

jonk
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  • This is just so precisely explained which is what I look for. To detail the cases even if they are thought to be obvious or not so important because a beginner like me wouldn't know them. I've a question here, when you said active-LO, you meant current from Vcc through resistor to pin right? and Passive-HI as in current from pin to shunt-LED while one end is sourcing from resistor in parallel to LED, right? If possible, I would also want your answer for my other asked question(s) as your explanation made certain things clear to me. Thanks – Peace Feb 19 '18 at 01:46
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It is also common to have a single NMOS for pulldown. And a high value resistor for pullup. This design is common in TTL type circuits. Since the source current has to flow through that resistor, you can only source a very small amount of current without voltage drop across that resistor becoming excessive.

Disadvantages of this design in addition to the low source current available, Is that the internal pullup resistor constantly uses power whenever the output pin is in a LOW state. But it simplifies IC design as you don't need a dedband circuit to ensure that there is never a time when both the NMOS and PMOS are on at the same time. Otherwise the IC will have an internal short circuit.

aredwood
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