4

First question

Whether we declare the array as scalar or vector, we can access each element bit by bit. For example, we can declare two arrays below.

reg scalar_array[0:9];
reg [0:9] vector_array;  

always @*
begin
  scalar_array[0] = 1'b1;
  vector_array[0] = 1'b1;
end

I would like to know if the difference exists between two declarations.

Second question

Also, when I declare the two-dimensional array like below, I could access the entire row using the indexing operator[] for the variable declared using a below syntax. 

reg[X:X] var_name [Y:Y];

However, I couldn't access the entire row when I declare the array using the below syntax.

reg var_name [X:X][Y:Y];

I would like to know how this concept can be synthesized on the hardware, and if they are both synthesizable, what is the difference between them. 

reg [0:9] vector_array_2d [0:15];
reg scalar_array_2d[0:9][0:15];
always @*
begin
  vector_array_2d[0] = 'd1;
  scalar_array_2d[0] = 'd1; //raise the error!! 
end
Paebbels
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ruach
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2 Answers2

1

For your first question, search for the difference between packed and unpacked arrays.

Your second question is a Verilog limitation with unpacked arrays - it only allows access to one array element at a time. SystemVerilog does not have this restriction. You can access an unpacked array as a whole, or select an entire dimension.

dave_59
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  • Thanks for an answer. However, it seems that Verilog doesn't support multiple packed dimensions. Vivado raise the error when I tried to declare the packed array like reg[3:0][4:0] packed_array; – ruach Feb 05 '18 at 05:23
  • Make sure you have turned on SystemVerilog, use a *.sv file extension. – dave_59 Feb 05 '18 at 05:25
  • this answer is specific to SystemVerilog, not Verilog – Aaron Thomas Aug 12 '20 at 16:19
  • ref https://stackoverflow.com/a/24344363/2658159 – Aaron Thomas Aug 12 '20 at 16:26
  • @AaronThomas SystemVerilog introduced the terminology "packed"and "unpacked", the functionality was the same as in Verilog. Although Verilog only allows a single packed dimension. – dave_59 Aug 12 '20 at 16:28
  • thank you for the clarification. would it be correct to say that for Verilog, a vector is a one-dimensional packed array? or is vector a different concept altogether? – Aaron Thomas Aug 12 '20 at 16:30
  • In the Verilog, a vector is a one-dimensional packed array. In SystemVerilog, a vector is any packed array or packed struct. Integral/vector/packed are different words for the same concept. – dave_59 Aug 12 '20 at 16:34
0

For the first question, the difference lies in how the register is to be treated - as either a bus (a single value, wider than one bit) or an array (multiple values, stored under one name). It seems a little bit philosophic, but this answer provides more detail.

For the second question, it may rely on the manufacturer or provider. For example, Xilinx Vivado will synthesize multi-dimensional arrays of up to two dimensions only (ref UG901).

Aaron Thomas
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