What is the role of ISA (Instruction Set Architecture) in the comp arch abstraction stack.

Question

I have programming background, and I recently started taking computer architecture course. Most of the lectures I see use the some sort of the layering as described in the following diagram explaining what will be covered in the course.

The question here is compiler (System software) takes care of converting high level/assembly code to machine code that can be understood by the processor. OS executes this code by managing the resources such as processor scheduling, memory management etc.. so what's the role of ISA layer here

1. What is the input interface to this layer (Machine code from OS)?
2. What is the output interface to this layer?

Image courtesy: http://theembeddedguy.com/2016/05/15/layers-of-abstraction/

Answer 1

The ISA is the level which a compiler targets (although optimisations are sensitive to the micro-architecture, particularly in terms of optimum scheduling). The ISA is a simplified but sufficient definition of the hardware interface.

The ISA describes the abstract behaviour of the underlying compute engine, and what the fundamental operations that can be encoded in machine code instructions. It will define what sort of registers the processor has, how they interact with memory, and what arithmetic operations are possible.

The ISA can also influence how easy it is to optimise the implementation (for example long pipelines, or wide issue), and may implement features which are intended to target specific high level languages (or simplify a compiler's task).

Along with the ISA, there will be architectural guarantees of ordering, exceptions, power control and access controls which also define the processor architecture. These are not relevant to a compiler (and frequently require intrinsics to access), but are critical to an OS (and sometimes applications).

Your diagram is a misleading abstraction, although each element is distinct, they don't interface to each other in the same way as a software stack would. Micro-architecture is for example influenced by feature size - both in terms of timing and costs - the gate level view is what designers think of when of when working on micro-arch).

To give a high level example of what an ISA is, consider how a fixed-length 32 bit instruction might be split up.

4 bits for instruction type (Load/Store, ALU, etc) 4 bits for instruction operation (Add/Sub, or addressing mode) 4 bits for operand 1 register 4 bits for operand 2 register 4 bits for destination register 4 bits for flow control 4 bits for constant input (e.g. operand shift) 4 more bits specific to the instruction

You would want to map these onto some superset of the functions you need for an efficient turing machine. Thus the ISA describes precisely what the machine code and assembly code represent (in a more-or-less 1:1 relation). Some instructions (NOP being the obvious example) can be achieved using a custom opcode, or a A=A|A type instruction if symmetry permits these.

In reference to the source of the diagram, in computer architecture, the micro-architecture would not generally be used to refer to the RAM, ROM and timers in a microcontroller. It would refer to how integer divide is implemented, how many instructions can execute per cycle, how many loads can be outstanding at a time - the sort of detail that is hard to observe in software at all.

Answer 2

The chart isn't about inputs and outputs at all, so the question as phrased is meaningless.

Any given system can be described at different levels of detail, and that is what the chart is about. Each layer describes the same system, but using different terms of reference.

For example, you could describe a web server at the highest level of abstraction as a computer that accepts HTTP requests and provides the requested data, where "HTTP request" is defined in a particular standards document as a TCP/IP connection carrying data in a particular format (the next level of detail).

The same system could be described in terms of the electromagnetic fields that it receives and transmits, along with how the electrical charges move within the patterns of metal and semiconductor within it. This would be the "physics" level of abstraction. It provides a lot of detail, but it's really too much detail to be useful in terms of understanding the high-level behavior.

In computer systems, the highest levels of abstraction are defined in software. In a sense, each layer of abstraction "runs on" the virtual machine defined by the next-lower level. The ISA is the level at which the transition from software to hardware is made: the ISA defines the hardware-software interface. At this level, the "virtual machine" is very general-purpose, because in most cases, we don't want to be defining different hardware machines for different applications.

In some cases, the ISA itself is an abstraction that runs on a lower-level hardware machine. There are microcoded machines that can load different versions of microcode to impelment different ISAs. The microcode processor is made of physical registers and gates.

I'm trying to read between the lines of your question and answer a question that you didn't really ask — is any of this helping?

Answer 3

I think the diagram is self-explanatory. Within the context and partitioning as presented in the original theembeddedguy.com article and the "input-output" paradigm, input for the layer pictured as "ISA" is the binary code generated at "Machine-Level Code". The ISA layer fetches the binary stream and parses it in accord with inner architecture of a processor. In the particular x86 architecture, it translates complex instructions (CISC) into simpler RISC-type formats in accord with inner processor micro-architecture. This is the "output".

The entire multi-level model is just an abstraction, and is not particularly useful in real world. The boundaries can be blurry, several more abstraction layers can be introduced, in implementations some layers can be combined, etc. The entire theembeddedguy.com article is an eclectic mix of terms, that likely explains the confusion.