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I am trying to make a good layout for the LAN9252 mac and STM32F7 controller, running at 80 MHz and I had to route data tracks with different lengths.

The question is should I use nets lengths matching tool in QSPI at 80 MHz?

kvazibog
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    STM32F7 from datasheet i see max SPI freq in any mode 54Mhz...I don't see QSPI support for it. – user19579 Oct 13 '18 at 03:22
  • Most processors dont support SPI at 80 MHz as user19570 said The application note about STM132F7 says that you can run it at 100 Mhz. Here are some details: https://www.st.com/content/ccc/resource/training/technical/product_training/group0/bf/e7/e9/12/cc/b4/4d/d9/STM32F7_Memory_QuadSPI/files/STM32F7_Memory_QuadSPI.pdf/jcr:content/translations/en.STM32F7_Memory_QuadSPI.pdf . Different lengths of SPI bus will not yield same data speed at same clock speed. You have to slow down the clock to match the slave connected at longest length. This clock speed may be less than 80 MHz. – Amit M Oct 24 '22 at 07:35

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Normally with QSPI at 80MHz I would say your primary concern should be to keep the QSPI clock line and the longest data line as short as possible. As long as you keep these to just a few centimeters you will generally be fine.

Actual data line length matching become a concern if you push up your clock frequency even further, or go for DDR, and your QSPI master implements more advanced techniques such as a feedback clock or adaptive sampling clock.

Timmy Brolin
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