What is a "half latch" in an FPGA?

Question

In a paper about radiation hard FPGAs I came across this sentence:

"Another concern regarding Virtex devices is half latches. Half latches are sometimes used within these devices for internal constants, as this is more efficient than using logic".

I have never heard about an FPGA device primitive called a "half latch". As far as I understand, it sounds like a hidden mechanism to "source" a constant '0' or '1' in the backend tools... Can anyone explain what exactly a "half latch" is, especially in the context of FPGAs, and how they can be used to save logic?

EDIT: The paper where I found this was A Comparison of Radiation-Hard and Radiation-Tolerant FPGAs for Space Applications

It's a fault that is reported in the design stage that requires corrective action https://www.slideserve.com/delilah/single-event-upsets-in-sram-fpgas due to accelerated stress, like a bit error internally except it latches and can make a tristate into an output for example — Tony Stewart EE75, Jan 25 '18 at 15:27
@TonyStewart.EEsince'75 Faults are used for internal constants? That doesn't make sense. — , Jan 25 '18 at 18:24
@TonyStewart.EEsince'75 That still doesn't make any sense in context. The presentation you linked to clearly depicts a "half latch" as a part of the FPGA, alongside other things like "config bits" and "BRAM". It isn't a fault; it's something which can be _affected by_ a fault. — , Jan 26 '18 at 00:30
They are design faults because a weak positive feedback creates a fault from a port going into tristate getting latched so Verilog reports them as half-latch faults then you have do low level diagnosis to prevent them — Tony Stewart EE75, Jan 26 '18 at 00:35
@TonyStewart.EEsince'75 I'm sorry, but that still isn't correct. Half-latches are not the same thing as _inferred_ latches, which may cause a synthesis _warning_ (not "fault"). A "fault" in the context of the presentation you linked is an electrical upset -- caused by a radiation event, for instance -- which disrupts logic running on the FPGA. — , Jan 27 '18 at 00:09
@duskwolf I was never referring to inferred latches, rather the same item described by Dmitry — Tony Stewart EE75, Jan 27 '18 at 01:46

Dmitry Grigoryev · Accepted Answer · 2018-01-26T23:36:40.067

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A half-latch is a gate with positive feedback implemented with a weak pull-up transistor:

schematic

^{simulate this circuit – Schematic created using CircuitLab}

When the input is actively driven, it overrides the signal coming from the weak pullup. When the input is in Z-state, the weak pullup can keep the logical "1" at the input (and "0" at the output) indefinitely. It will not keep the opposite state reliably, hence "half-latch".

Why would someone want a half-latch instead of a full latch? For some signals it doesn't make sense to be able to store both constants. For example, a D-flipflop can have enable input only latched high, and reset input only latched low, otherwise it will simply be eliminated during synthesis. That's the kind of signals for which half-latches are used: they are either latched to default value, or driven by interconnect.

edited Jan 26 '18 at 23:36

answered Jan 25 '18 at 15:56

Dmitry Grigoryev

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So you're supposed to drive the input high for a moment before floating it, or you will end up with a metastable state that will eventually but unpredictably flip? – hmakholm left over Monica Jan 25 '18 at 23:56
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@HenningMakholm Yes, the FPGA drives all half-latches before each programming cycle. – Dmitry Grigoryev Jan 26 '18 at 21:37
That sounds like a significant complication of whichever circuitry supplies the input, just to save a single transistor. If you could write something about why on earth that would be worth it, I think it would improve the answer. – hmakholm left over Monica Jan 26 '18 at 21:49
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@HenningMakholm Why do you think a half-latches only save a single transistor? AFAIK they are used as constants which otherwise would have to be encoded in LUTs. – Dmitry Grigoryev Jan 26 '18 at 23:03
A fully functional latch would only need a single weak NMOS in addition to your diagram to pull the input down when the output is high, right? I don't know what a LUT is -- can you say something in your answer about how "used as constants" works if the only thing it can store reliably is an 1? How are these things _used_? – hmakholm left over Monica Jan 26 '18 at 23:07
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@HenningMakholm LUT is an acronym for look-up table. I have added an example. – Dmitry Grigoryev Jan 26 '18 at 23:38
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@HenningMakholm And BTW, if you use a full latch, you still have to drive it once to get it into a predictable state, right? – Dmitry Grigoryev Jan 26 '18 at 23:47
Ah, so if I understand you correctly, this is for use in a case where in the design phase you can _either_ connect the input signal (in which case you're supposed to be driving it _all the time_ rather than sometimes tri-stating it), _or_ leave it unconnected entirely, in which case the half-latch supplies a default? – hmakholm left over Monica Jan 27 '18 at 00:11
(At first your description sounded to me like the input was supposed to be something like a tri-state common line where some of the time nobody might be driving it). – hmakholm left over Monica Jan 27 '18 at 00:13
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@Dimitry: Nice answer. Do I understand correctly, that half latches are (commonly?) used in FPGA interconnect matrices? And by sourcing constant from "within" the interconnect matrices no logic resources must be used. – andrsmllr Jan 27 '18 at 11:21
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@damage Exactly. – Dmitry Grigoryev Jan 27 '18 at 12:16

score -2 · Answer 2 · answered Jan 25 '18 at 15:26

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It seems they provide the logic for keeping constants.

Since they are not observable, can only be initialised once (so only reconfigurable after device initialisation), they do not consume a full LUT and they are much simpler, nevertheless usefull.

answered Jan 25 '18 at 15:26

gommer

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I saw that abstract text when I searched google, too. It doesn't properly explain them as per OP's question, nor lead them to a datasheet example. Downvoting. – TonyM Jan 25 '18 at 15:34
If its a different structure of the FPGA and less than a full LUT, with a few more more specifics, then please explain how it does not answer the question 'what is it' and as for 'how it saves logic', that's also answered. – gommer Jan 25 '18 at 15:56

What is a "half latch" in an FPGA?

2 Answers2