2

At the moment ISE limits generate loops to 64. When I go above, it produces the error:

Loop count limit exceeded. Condition is never false.

I found that the loop_iteration_limit option should be added to the corresponding project .xst file. However, when I add the line -loop_iteration_limit 10000 to the .xst file, and recompile, that line disappears.

How can I do long loops in Verilog with ISE? (The reason I want to do this is to instantiate many copies of an inverter to try to heat up my FPGA and test the power supply.)

Randomblue
  • 10,953
  • 29
  • 105
  • 178
  • 1
    The optimiser will likely just get rid of all your inverters and replace them with a single one (or none if you had an even number to start with) – Martin Thompson Jul 06 '12 at 15:01
  • @MartinThompson: I want to activate as much logic in the FPGA as possible at the same time. Any suggestions? – Randomblue Jul 06 '12 at 15:03
  • 1
    In that case, I'd be tempted to change your question to ask precisely that... – Martin Thompson Jul 06 '12 at 15:05
  • @MartinThompson: I [already have](http://electronics.stackexchange.com/questions/32440/stress-testing-an-fpgas-power-supply) such a question. – Randomblue Jul 06 '12 at 15:10

2 Answers2

2

How about creating a massive shift register and clocking that as fast as possible with alternating ones and zeros going in?

signal sr:std_logic_vector(10000 downto 0); -- tune the length of this to suit your device
process
begin
   wait until rising_edge(clk);
   sr <= sr(sr'high-1 downto 0) & input_signal;
end process;

That won't use much much LUT logic though. Nor test any other embedded blocks like BRAMs and DSPs.

Martin Thompson
  • 8,439
  • 1
  • 23
  • 44
  • To make the massive shift register, don't I need a massive `generate` loop also? – Randomblue Jul 09 '12 at 09:20
  • 1
    Thanks a lot! I don't know VHDL. Could you please provide a Verilog equivalent? – Randomblue Jul 09 '12 at 11:58
  • 1
    Come now @Randomblue, search for "verilog shift register", and you find: http://asic.co.in/Index_files/verilogexamples.htm#link20, and http://www.doulos.com/knowhow/verilog_designers_guide/models/shift_register/ amongst others! – Martin Thompson Jul 09 '12 at 12:55
0

“That won't use much much LUT logic though. Nor test any other embedded blocks like BRAMs and DSPs.”

I think making a massive shift register with alternating ones and zeros is an elegant solution. If you play your cards right and avoid explicit sets/resets or directly making use of individual bits, the synthesizer may infer that it can make use of tight SRL-based (LUT-based) shift registers to save space, but you can also explicitly request SRL-based shift registers by making use of SRL16E or SRLC32E library primitives to build up a larger structure. Furthermore, if you cut things up into 34-bit shift register pieces, you’ll be able to make your structure thread through all of the available LUTs and FFs quite nicely, as suggested by the Verilog code snippet below which will fit snugly inside precisely one Spartan-6 or 7-series slice:

wire [4:0] bits; // Shift interconnect: 0->1->2->3->4 SRL16E #(.INIT(16'hAAAA)) // First 16-bit LUT-based shift register srl1 ( .CLK(clock), .CE(1'b1), .A3(1'b1), .A2(1'b1), .A1(1'b1), .A0(1'b1), .D(bits[0]), .Q(bits[1]) ); FDE #(.INIT(1'b1)) // First 1-bit FF-based shift register fde1 ( .C(clock), .CE(1'b1), .D(bits[1]), .Q(bits[2]) ); SRL16E #(.INIT(16'h5555)) // Second 16-bit LUT-based shift register srl2 ( .CLK(clock), .CE(1'b1), .A3(1'b1), .A2(1'b1), .A1(1'b1), .A0(1'b1), .D(bits[2]), .Q(bits[3]) ); FDE #(.INIT(1'b0)) // Second 1-bit FF-based shift register fde2 ( .C(clock), .CE(1'b1), .D(bits[3]), .Q(bits[4]) );

XAPP52 "Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequences Generators" has several examples of this approach.

For more general info about SRL16E and SRLC32E, consult:
UG768 "Xilinx 7 Series FPGA Libraries Guide for HDL Designs"
UG615 "Spartan-6 Libraries Guide for HDL Designs".

To pull in RAM blocks and DSPs you would need additional circuitry, possibly feeding collections of shift register feeds to seed them with data that is constantly changing. Dual-ported RAM blocks could be used to build up a large FIFO chain that is 1-bit wide and N-stages deep (depending on the resources available in your FPGA). Thus, you could use the RAM blocks to extend your shift register chain to truly epic lengths.

Bert Sierra
  • 11
  • 3